- asl zp/zp,x/abs/abs,x

- ror zp/zp,x/abs supported.

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index 296a7f9..53caf50 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -622,7 +622,7 @@ end procedure;
                 carry_out <= c;
 
             elsif instruction (7 downto 5) = "111" then
-                d_print("sbc");
+                --d_print("sbc");
                 sel <= ALU_SBC;
                 d1 <= acc_out;
                 d2 <= int_d_bus;
@@ -672,19 +672,19 @@ end procedure;
 
 
             if instruction (7 downto 5) = "000" then
-                d_print("asl");
+                --d_print("asl");
                 sel <= ALU_ASL;
                 set_nz;
                 carry_out <= c;
 
             elsif instruction (7 downto 5) = "001" then
-                d_print("rol");
+                --d_print("rol");
                 sel <= ALU_ROL;
                 set_nz;
                 carry_out <= c;
 
             elsif instruction (7 downto 5) = "010" then
-                d_print("lsr");
+                --d_print("lsr");
                 sel <= ALU_LSR;
                 set_nz;
                 carry_out <= c;
@@ -709,7 +709,7 @@ end procedure;
 
         elsif instruction (1 downto 0) = "00" then
             if instruction (7 downto 5) = "001" then
-                d_print("bit");
+                --d_print("bit");
                 sel <= ALU_BIT;
                 d1 <= acc_out;
                 d2 <= int_d_bus;

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 1744fc7..dd81cb9 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -1857,18 +1857,34 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#06#, dsize) then
                     --zp
                     d_print("asl");
+                    a4_zp;
+                    if exec_cycle = T4 then
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#16#, dsize) then
                     --zp, x
                     d_print("asl");
+                    a4_zp_x;
+                    if exec_cycle = T5 then
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#0e#, dsize) then
                     --abs
                     d_print("asl");
+                    a4_abs;
+                    if exec_cycle = T5 then
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#1e#, dsize) then
                     --abs, x
                     d_print("asl");
+                    a4_abs_x;
+                    if exec_cycle = T6 then
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#c6#, dsize) then
                     --zp
@@ -2001,18 +2017,26 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#66#, dsize) then
                     --zp
                     d_print("ror");
---                    a4_zp;
---                    if exec_cycle = T4 then
---                        set_nzc_from_alu;
---                    end if;
+                    a4_zp;
+                    if exec_cycle = T4 then
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#76#, dsize) then
                     --zp, x
                     d_print("ror");
+                    a4_zp_x;
+                    if exec_cycle = T5 then
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#6e#, dsize) then
                     --abs
                     d_print("ror");
+                    a4_abs;
+                    if exec_cycle = T5 then
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#7e#, dsize) then
                     --abs, x

diff --git a/tools/test-image/sample1.asm b/tools/test-image/sample1.asm
index 4e001cb..e72bf13 100644 (file)
--- a/tools/test-image/sample1.asm
+++ b/tools/test-image/sample1.asm
@@ -574,6 +574,29 @@ boundary_3_4:
     stx $0722\r
     inc $06be, x\r
 \r
+    ;;ror zp/zp,x/abs\r
+    lda #$02\r
+    ldx #$e4\r
+    sta $88\r
+    ror $a4, x\r
+    ror $a4, x\r
+    ror $a4, x\r
+\r
+    ldx #$64\r
+    stx $0722\r
+    ror $0722\r
+\r
+    ;;asl zp/zp,x/abs/abs,x\r
+    lda #$40\r
+    ldx #$e4\r
+    sta $88\r
+    asl $88\r
+    asl $a4, x\r
+    asl $a4, x\r
+\r
+    ldx #$64\r
+    stx $0722\r
+    asl $06be,x\r
 \r
     ;;done...\r
     ;;infinite loop.\r