carry_out <= c;
elsif instruction (7 downto 5) = "111" then
- d_print("sbc");
+ --d_print("sbc");
sel <= ALU_SBC;
d1 <= acc_out;
d2 <= int_d_bus;
if instruction (7 downto 5) = "000" then
- d_print("asl");
+ --d_print("asl");
sel <= ALU_ASL;
set_nz;
carry_out <= c;
elsif instruction (7 downto 5) = "001" then
- d_print("rol");
+ --d_print("rol");
sel <= ALU_ROL;
set_nz;
carry_out <= c;
elsif instruction (7 downto 5) = "010" then
- d_print("lsr");
+ --d_print("lsr");
sel <= ALU_LSR;
set_nz;
carry_out <= c;
elsif instruction (1 downto 0) = "00" then
if instruction (7 downto 5) = "001" then
- d_print("bit");
+ --d_print("bit");
sel <= ALU_BIT;
d1 <= acc_out;
d2 <= int_d_bus;
elsif instruction = conv_std_logic_vector(16#06#, dsize) then
--zp
d_print("asl");
+ a4_zp;
+ if exec_cycle = T4 then
+ set_nzc_from_alu;
+ end if;
elsif instruction = conv_std_logic_vector(16#16#, dsize) then
--zp, x
d_print("asl");
+ a4_zp_x;
+ if exec_cycle = T5 then
+ set_nzc_from_alu;
+ end if;
elsif instruction = conv_std_logic_vector(16#0e#, dsize) then
--abs
d_print("asl");
+ a4_abs;
+ if exec_cycle = T5 then
+ set_nzc_from_alu;
+ end if;
elsif instruction = conv_std_logic_vector(16#1e#, dsize) then
--abs, x
d_print("asl");
+ a4_abs_x;
+ if exec_cycle = T6 then
+ set_nzc_from_alu;
+ end if;
elsif instruction = conv_std_logic_vector(16#c6#, dsize) then
--zp
elsif instruction = conv_std_logic_vector(16#66#, dsize) then
--zp
d_print("ror");
--- a4_zp;
--- if exec_cycle = T4 then
--- set_nzc_from_alu;
--- end if;
+ a4_zp;
+ if exec_cycle = T4 then
+ set_nzc_from_alu;
+ end if;
elsif instruction = conv_std_logic_vector(16#76#, dsize) then
--zp, x
d_print("ror");
+ a4_zp_x;
+ if exec_cycle = T5 then
+ set_nzc_from_alu;
+ end if;
elsif instruction = conv_std_logic_vector(16#6e#, dsize) then
--abs
d_print("ror");
+ a4_abs;
+ if exec_cycle = T5 then
+ set_nzc_from_alu;
+ end if;
elsif instruction = conv_std_logic_vector(16#7e#, dsize) then
--abs, x