target-arm queue:
* Start of conversion of Neon insns to decodetree
* versal board: support SD and RTC
* Implement ARMv8.2-TTS2UXN
* Make VQDMULL undefined when U=1
* Some minor code cleanups
# gpg: Signature made Mon 04 May 2020 13:32:08 BST
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-
20200504: (39 commits)
target/arm: Move gen_ function typedefs to translate.h
target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree
target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree
target/arm: Convert Neon 3-reg-same comparisons to decodetree
target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree
target/arm: Convert Neon 3-reg-same logic ops to decodetree
target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree
target/arm: Convert Neon 'load/store single structure' to decodetree
target/arm: Convert Neon 'load single structure to all lanes' to decodetree
target/arm: Convert Neon load/store multiple structures to decodetree
target/arm: Convert VFM[AS]L (scalar) to decodetree
target/arm: Convert V[US]DOT (scalar) to decodetree
target/arm: Convert VCMLA (scalar) to decodetree
target/arm: Convert VFM[AS]L (vector) to decodetree
target/arm: Convert V[US]DOT (vector) to decodetree
target/arm: Convert VCADD (vector) to decodetree
target/arm: Convert VCMLA (vector) to decodetree
target/arm: Add stubs for AArch32 Neon decodetree
target/arm: Don't allow Thumb Neon insns without FEATURE_NEON
target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>