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drm/i915/icp: Add Wa_14010685332
authorMatt Roper <matthew.d.roper@intel.com>
Fri, 1 May 2020 21:37:01 +0000 (14:37 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Tue, 5 May 2020 21:26:46 +0000 (14:26 -0700)
We need to toggle a SDE chicken bit on and then off as the final
step when disabling interrupts in preparation for runtime suspend.

Bspec: 33450
Bspec: 8402
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200501213701.371443-1-matthew.d.roper@intel.com
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_reg.h

index 0b8b0c0..ea4c877 100644 (file)
@@ -2870,6 +2870,14 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
 
        if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
                GEN3_IRQ_RESET(uncore, SDE);
+
+       /* Wa_14010685332:icl */
+       if (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) {
+               intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
+                                SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
+               intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
+                                SBCLK_RUN_REFCLK_DIS, 0);
+       }
 }
 
 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
index f23a18e..fde54b8 100644 (file)
@@ -8573,6 +8573,7 @@ enum {
 #define  FDI_BC_BIFURCATION_SELECT     (1 << 12)
 #define  CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
 #define  CHASSIS_CLK_REQ_DURATION(x)   ((x) << 8)
+#define  SBCLK_RUN_REFCLK_DIS          (1 << 7)
 #define  SPT_PWM_GRANULARITY           (1 << 0)
 #define SOUTH_CHICKEN2         _MMIO(0xc2004)
 #define  FDI_MPHY_IOSFSB_RESET_STATUS  (1 << 13)