drm/amdgpu: abstract gart aperture initialization for gfxhub/mmhub

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index be3f634..8975834 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -55,6 +55,25 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
               upper_32_bits(value));
 }
 
+static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
+{
+       gfxhub_v1_0_init_gart_pt_regs(adev);
+
+       WREG32(SOC15_REG_OFFSET(GC, 0,
+                               mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
+               (u32)(adev->mc.gtt_start >> 12));
+       WREG32(SOC15_REG_OFFSET(GC, 0,
+                               mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
+               (u32)(adev->mc.gtt_start >> 44));
+
+       WREG32(SOC15_REG_OFFSET(GC, 0,
+                               mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
+               (u32)(adev->mc.gtt_end >> 12));
+       WREG32(SOC15_REG_OFFSET(GC, 0,
+                               mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
+               (u32)(adev->mc.gtt_end >> 44));
+}
+
 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
        u32 tmp;
@@ -62,9 +81,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
        u32 i;
 
        /* Program MC. */
-       gfxhub_v1_0_init_gart_pt_regs(adev);
+       gfxhub_v1_0_init_gart_aperture_regs(adev);
 
-       /* Update configuration */
        WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
                adev->mc.vram_start >> 18);
        WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
@@ -165,21 +183,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
                            0);
        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
 
-       /* setup context0 */
-       WREG32(SOC15_REG_OFFSET(GC, 0,
-                               mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
-               (u32)(adev->mc.gtt_start >> 12));
-       WREG32(SOC15_REG_OFFSET(GC, 0,
-                               mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
-               (u32)(adev->mc.gtt_start >> 44));
-
-       WREG32(SOC15_REG_OFFSET(GC, 0,
-                               mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
-               (u32)(adev->mc.gtt_end >> 12));
-       WREG32(SOC15_REG_OFFSET(GC, 0,
-                               mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
-               (u32)(adev->mc.gtt_end >> 44));
-
        WREG32(SOC15_REG_OFFSET(GC, 0,
                                mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
                (u32)(adev->dummy_page.addr >> 12));

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index d720e16..9ca2360 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -66,6 +66,25 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
               upper_32_bits(value));
 }
 
+static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
+{
+       mmhub_v1_0_init_gart_pt_regs(adev);
+
+       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+                               mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
+               (u32)(adev->mc.gtt_start >> 12));
+       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+                               mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
+               (u32)(adev->mc.gtt_start >> 44));
+
+       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+                               mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
+               (u32)(adev->mc.gtt_end >> 12));
+       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+                               mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
+               (u32)(adev->mc.gtt_end >> 44));
+}
+
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
        u32 tmp;
@@ -75,6 +94,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 
        /* Program MC. */
        mmhub_v1_0_init_gart_pt_regs(adev);
+       mmhub_v1_0_init_gart_aperture_regs(adev);
 
        /* Update configuration */
        WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
@@ -176,21 +196,6 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
                            0);
        WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);
 
-       /* setup context0 */
-       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-                               mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
-               (u32)(adev->mc.gtt_start >> 12));
-       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-                               mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
-               (u32)(adev->mc.gtt_start >> 44));
-
-       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-                               mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
-               (u32)(adev->mc.gtt_end >> 12));
-       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-                               mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
-               (u32)(adev->mc.gtt_end >> 44));
-
        WREG32(SOC15_REG_OFFSET(MMHUB, 0,
                                mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
                (u32)(adev->dummy_page.addr >> 12));