vdda-supply = <&vdda>;
vref-supply = <&vdda>;
status = "okay";
+};
- adc1: adc@0 {
- st,min-sample-time-nsecs = <5000>;
- st,adc-channels = <0>;
- status = "okay";
+&adc1 {
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
};
+};
- adc2: adc@100 {
- st,adc-channels = <1>;
- st,min-sample-time-nsecs = <5000>;
- status = "okay";
+&adc2 {
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
};
};
vdda-supply = <&vdda>;
vref-supply = <&vdda>;
status = "okay";
+};
- adc1: adc@0 {
- st,adc-channels = <0 1 6>;
- st,min-sample-time-nsecs = <5000>;
- status = "okay";
+&adc1 {
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
};
- adc2: adc@100 {
- st,adc-channels = <0 1 2>;
- st,min-sample-time-nsecs = <5000>;
- status = "okay";
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <5000>;
+ };
+};
+
+&adc2 {
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ channel@2 {
+ reg = <2>;
+ st,min-sample-time-ns = <5000>;
};
};