[ARM GlobalISel] Add inst selector tests for G_FNEG s32 and s64

G_FNEG is already handled by the TableGen'erated code. Just add a few
tests to make sure everything works as expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322170 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
index a683d3a..f328a93 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
@@ -30,9 +30,14 @@
 
   define void @test_movti16_0xffff() #2 { ret void }
 
+  define void @test_vnmuls() #3 { ret void }
+  define void @test_vnmuls_reassociate() #3 { ret void }
+  define void @test_vnmuld() #3 { ret void }
+
   attributes #0 = { "target-features"="+v6" }
   attributes #1 = { "target-features"="-v6" }
   attributes #2 = { "target-features"="+v6t2" }
+  attributes #3 = { "target-features"="+vfp2" }
 ...
 ---
 name:            test_mla
@@ -863,3 +868,96 @@ body:             |
     BX_RET 14, %noreg, implicit %r0
     ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
+---
+name:            test_vnmuls
+# CHECK-LABEL: name: test_vnmuls
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+body:             |
+  bb.0:
+    liveins: %s0, %s1
+
+    %0(s32) = COPY %s0
+    %1(s32) = COPY %s1
+    ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
+    ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
+
+    %2(s32) = G_FMUL %0, %1
+    %3(s32) = G_FNEG %2
+    ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, %noreg
+
+    %s0 = COPY %3(s32)
+    ; CHECK: %s0 = COPY [[VREGR]]
+
+    BX_RET 14, %noreg, implicit %s0
+    ; CHECK: BX_RET 14, %noreg, implicit %s0
+...
+---
+name:            test_vnmuls_reassociate
+# CHECK-LABEL: name: test_vnmuls_reassociate
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+body:             |
+  bb.0:
+    liveins: %s0, %s1
+
+    %0(s32) = COPY %s0
+    %1(s32) = COPY %s1
+    ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
+    ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
+
+    %2(s32) = G_FNEG %0
+    %3(s32) = G_FMUL %1, %2
+    ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, %noreg
+
+    %s0 = COPY %3(s32)
+    ; CHECK: %s0 = COPY [[VREGR]]
+
+    BX_RET 14, %noreg, implicit %s0
+    ; CHECK: BX_RET 14, %noreg, implicit %s0
+...
+---
+name:            test_vnmuld
+# CHECK-LABEL: name: test_vnmuld
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+body:             |
+  bb.0:
+    liveins: %d0, %d1
+
+    %0(s64) = COPY %d0
+    %1(s64) = COPY %d1
+    ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+
+    %2(s64) = G_FMUL %0, %1
+    %3(s64) = G_FNEG %2
+    ; CHECK: [[VREGR:%[0-9]+]]:dpr = VNMULD [[VREGX]], [[VREGY]], 14, %noreg
+
+    %d0 = COPY %3(s64)
+    ; CHECK: %d0 = COPY [[VREGR]]
+
+    BX_RET 14, %noreg, implicit %d0
+    ; CHECK: BX_RET 14, %noreg, implicit %d0
+...

diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index eaac829..490ffa8 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -24,6 +24,9 @@
   define void @test_fdiv_s32() #0 { ret void }
   define void @test_fdiv_s64() #0 { ret void }
 
+  define void @test_fneg_s32() #0 { ret void }
+  define void @test_fneg_s64() #0 { ret void }
+
   define void @test_sub_s32() { ret void }
   define void @test_sub_imm_s32() { ret void }
   define void @test_sub_rev_imm_s32() { ret void }
@@ -608,6 +611,59 @@ body:             |
     ; CHECK: BX_RET 14, %noreg, implicit %d0
 ...
 ---
+name:            test_fneg_s32
+# CHECK-LABEL: name: test_fneg_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+body:             |
+  bb.0:
+    liveins: %s0
+
+    %0(s32) = COPY %s0
+    ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+
+    %1(s32) = G_FNEG %0
+    ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14, %noreg
+
+    %s0 = COPY %1(s32)
+    ; CHECK: %s0 = COPY [[VREGSUM]]
+
+    BX_RET 14, %noreg, implicit %s0
+    ; CHECK: BX_RET 14, %noreg, implicit %s0
+...
+---
+name:            test_fneg_s64
+# CHECK-LABEL: name: test_fneg_s64
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+body:             |
+  bb.0:
+    liveins: %d0
+
+    %0(s64) = COPY %d0
+    ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+
+    %1(s64) = G_FNEG %0
+    ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14, %noreg
+
+    %d0 = COPY %1(s64)
+    ; CHECK: %d0 = COPY [[VREGSUM]]
+
+    BX_RET 14, %noreg, implicit %d0
+    ; CHECK: BX_RET 14, %noreg, implicit %d0
+...
+---
 name:            test_sub_s32
 # CHECK-LABEL: name: test_sub_s32
 legalized:       true