Apply Paul Brook's patch to implement armv6k instructions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 1d96352..231242b 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,9 @@
+2004-09-30  Paul Brook  <paul@codesourcery.com>
+
+       * reloc.c: Add BFD_RELOC_ARM_SMI.
+       * bfd-in2.h: Regenerate.
+       * libbfd.h: Ditto.
+
 2004-09-24  Alan Modra  <amodra@bigpond.net.au>
 
        * dwarf2.c (_bfd_dwarf2_find_nearest_line): Add output section

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 4be38cf..6feb83e 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2618,6 +2618,7 @@ field in the instruction.  */
   BFD_RELOC_ARM_ADRL_IMMEDIATE,
   BFD_RELOC_ARM_OFFSET_IMM,
   BFD_RELOC_ARM_SHIFT_IMM,
+  BFD_RELOC_ARM_SMI,
   BFD_RELOC_ARM_SWI,
   BFD_RELOC_ARM_MULTI,
   BFD_RELOC_ARM_CP_OFF_IMM,

diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index abe6a2a..c079a6a 100644 (file)
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1111,6 +1111,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_ARM_ADRL_IMMEDIATE",
   "BFD_RELOC_ARM_OFFSET_IMM",
   "BFD_RELOC_ARM_SHIFT_IMM",
+  "BFD_RELOC_ARM_SMI",
   "BFD_RELOC_ARM_SWI",
   "BFD_RELOC_ARM_MULTI",
   "BFD_RELOC_ARM_CP_OFF_IMM",

diff --git a/bfd/reloc.c b/bfd/reloc.c
index 8356b60..0069841 100644 (file)
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -2560,6 +2560,8 @@ ENUMX
 ENUMX
   BFD_RELOC_ARM_SHIFT_IMM
 ENUMX
+  BFD_RELOC_ARM_SMI
+ENUMX
   BFD_RELOC_ARM_SWI
 ENUMX
   BFD_RELOC_ARM_MULTI

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 462165c..6d75eee 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2004-09-30  Paul Brook  <paul@codesourcery.com>
+
+       * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
+       (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
+
 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 
        * avr.h: Add support for

diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 6ccccbd..dd90e2a 100644 (file)
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -32,6 +32,8 @@
 #define ARM_EXT_V5E     0x00000400     /* DSP Double transfers.   */
 #define ARM_EXT_V5J     0x00000800     /* Jazelle extension.      */
 #define ARM_EXT_V6       0x00001000     /* ARM V6.                 */
+#define ARM_EXT_V6K      0x00002000     /* ARM V6K.                */
+#define ARM_EXT_V6Z      0x00004000     /* ARM V6Z.                */
 
 /* Co-processor space extensions.  */
 #define ARM_CEXT_XSCALE   0x00800000   /* Allow MIA etc.          */
@@ -60,6 +62,9 @@
 #define ARM_ARCH_V5TE  (ARM_ARCH_V5TExP | ARM_EXT_V5E)
 #define ARM_ARCH_V5TEJ (ARM_ARCH_V5TE  | ARM_EXT_V5J)
 #define ARM_ARCH_V6     (ARM_ARCH_V5TEJ | ARM_EXT_V6)
+#define ARM_ARCH_V6K    (ARM_ARCH_V6    | ARM_EXT_V6K)
+#define ARM_ARCH_V6Z    (ARM_ARCH_V6    | ARM_EXT_V6Z)
+#define ARM_ARCH_V6ZK   (ARM_ARCH_V6    | ARM_EXT_V6K | ARM_EXT_V6Z)
 
 /* Processors with specific extensions in the co-processor space.  */
 #define ARM_ARCH_XSCALE        (ARM_ARCH_V5TE  | ARM_CEXT_XSCALE)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f4eebbb..cf49121 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2004-09-30  Paul Brook  <paul@codesourcery.com>
+
+       * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
+       * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
+
 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 
        * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index e918daf..44cdeac 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1,5 +1,5 @@
 /* Instruction printing code for the ARM
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
    Modification by James G. Smith (jsmith@cygnus.co.uk)
@@ -900,6 +900,15 @@ print_insn_arm (pc, info, given)
                        }
                        break;
 
+                     case 'e':
+                       {
+                         int imm;
+
+                         imm = (given & 0xf) | ((given & 0xfff00) >> 4);
+                         func (stream, "%d", imm);
+                       }
+                       break;
+
                      default:
                        abort ();
                      }

diff --git a/opcodes/arm-opc.h b/opcodes/arm-opc.h
index 4b52f13..531f458 100644 (file)
--- a/opcodes/arm-opc.h
+++ b/opcodes/arm-opc.h
@@ -1,6 +1,6 @@
 /* Opcode table for the ARM.
 
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2003
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2003, 2004
    Free Software Foundation, Inc.
    
    This program is free software; you can redistribute it and/or modify
@@ -18,18 +18,19 @@
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 
-struct arm_opcode {
-    unsigned long value, mask; /* recognise instruction if (op&mask)==value */
-    char *assembler;           /* how to disassemble this instruction */
+struct arm_opcode
+{
+  unsigned long value, mask;   /* Recognise instruction if (op&mask)==value.  */
+  char *assembler;             /* How to disassemble this instruction.  */
 };
 
 struct thumb_opcode
 {
-    unsigned short value, mask;        /* recognise instruction if (op&mask)==value */
-    char * assembler;          /* how to disassemble this instruction */
+  unsigned short value, mask;  /* Recognise instruction if (op&mask)==value.  */
+  char * assembler;            /* How to disassemble this instruction.  */
 };
 
-/* format of the assembler string :
+/* Format of the assembler string :
    
    %%                  %
    %<bitfield>d                print the bitfield in decimal
@@ -82,10 +83,10 @@ Thumb specific format options:
    %<bitfield>W         print (bitfield * 4) as a decimal
    %<bitfield>H         print (bitfield * 2) as a decimal
    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
-*/
+   %e                   print arm SMI operand (bits 0..7,8..19).  */
 
 /* Note: There is a partial ordering in this table - it must be searched from
-   the top to obtain a correct match. */
+   the top to obtain a correct match.  */
 
 static const struct arm_opcode arm_opcodes[] =
 {
@@ -98,7 +99,26 @@ static const struct arm_opcode arm_opcodes[] =
     {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
     {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
 
-    /* ARM V6 instructions. */
+    /* ARM V6Z instructions.  */
+    {0x01600070, 0x0ff000f0, "smi%c\t%e"},
+    
+    /* ARM V6K instructions.  */
+    {0xf57ff01f, 0xffffffff, "clrex"},
+    {0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"},
+    {0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"},
+    {0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"},
+    {0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"},
+    {0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"},
+    {0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"},
+
+    /* ARM V6K NOP hints.  */
+    {0x0320f001, 0x0fffffff, "yield"},
+    {0x0320f002, 0x0fffffff, "wfe"},
+    {0x0320f003, 0x0fffffff, "wfi"},
+    {0x0320f004, 0x0fffffff, "sev"},
+    {0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
+
+    /* ARM V6 instructions.  */
     {0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
     {0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
     {0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"},