[VM][FM7][MB61VH010] Add aving state.
[VM][FM7] Improve saving states.
[VM][FM7] Fix some other bugs.
#endif
#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
mode400line = false;
+ alu->write_signal(SIG_ALU_400LINE, 0x00, 0xff);
mode256k = false;
monitor_ram = false;
monitor_ram_using = false;
vram_wrote = true;
clr_count = 0;
-#if defined(_FM77AV_VARIANTS)
- //memset(submem_hidden, 0x00, sizeof(submem_hidden));
- //register_event(this, EVENT_FM7SUB_VSTART, 1.0, false, &vstart_event_id);
-#endif
firq_mask = (mainio->read_signal(FM7_MAINIO_KEYBOARDIRQ_MASK) != 0) ? false : true;
key_firq_req = false; //firq_mask = true;
do_attention = false;
mainio->write_signal(FM7_MAINIO_SUB_ATTENTION, 0x00, 0x01);
+#if defined(_FM77AV_VARIANTS)
+ alu->write_signal(SIG_ALU_X_WIDTH, 80, 0xffff);
+ alu->write_signal(SIG_ALU_Y_HEIGHT, 200, 0xffff);
+ alu->write_signal(SIG_ALU_400LINE, 0, 0xffffffff);
+#endif
subcpu->reset();
//subcpu->write_signal(SIG_CPU_BUSREQ, 1, 1);
//reset_cpuonly();
}
if(oldmode != display_mode) {
for(y = 0; y < 400; y++) memset(emu->screen_buffer(y), 0x00, 640 * sizeof(scrntype));
+ alu->write_signal(SIG_ALU_X_WIDTH, (mode320 || mode256k) ? 40 : 80, 0xffff);
+ alu->write_signal(SIG_ALU_Y_HEIGHT, (display_mode == DISPLAY_MODE_8_400L) ? 400 : 200, 0xffff);
}
+ alu->write_signal(SIG_ALU_400LINE, (mode_400line) ? 0xff : 0x00, 0xff);
}
#endif
break;
}
mode320 = flag;
display_mode = (mode320) ? DISPLAY_MODE_4096 : DISPLAY_MODE_8_200L;
+ alu->write_signal(SIG_ALU_X_WIDTH, (mode320 || mode256k) ? 40 : 80, 0xffff);
+ alu->write_signal(SIG_ALU_Y_HEIGHT, (display_mode == DISPLAY_MODE_8_400L) ? 400 : 200, 0xffff);
}
#else
if(mode320 != flag) {
}
mode320 = flag;
display_mode = (mode320 == true) ? DISPLAY_MODE_4096 : DISPLAY_MODE_8_200L;
+ alu->write_signal(SIG_ALU_X_WIDTH, (mode320) ? 40 : 80, 0xffff);
+ alu->write_signal(SIG_ALU_Y_HEIGHT, 200, 0xffff);
vram_wrote = true;
//printf("MODE320: %d\n", display_mode);
#endif
{
}
-#define STATE_VERSION 1
+#define STATE_VERSION 2
void DISPLAY::save_state(FILEIO *state_fio)
{
int i;
- state_fio->FputUint32(STATE_VERSION);
- state_fio->FputInt32(this_device_id);
-
- state_fio->FputInt32(clr_count);
- state_fio->FputBool(halt_flag);
- state_fio->FputInt32(active_page);
- state_fio->FputBool(sub_busy);
- state_fio->FputBool(sub_run);
- state_fio->FputBool(crt_flag);
- state_fio->FputBool(vram_wrote);
- state_fio->FputBool(is_cyclesteal);
-
- state_fio->FputUint8(kanji1_addr.b.l);
- state_fio->FputUint8(kanji1_addr.b.h);
-
- state_fio->FputBool(do_attention);
- state_fio->FputBool(irq_backup);
- state_fio->FputBool(clock_fast);
-
+ state_fio->FputUint32_BE(STATE_VERSION);
+ state_fio->FputInt32_BE(this_device_id);
+
+ {
+ state_fio->FputInt32_BE(clr_count);
+ state_fio->FputBool(halt_flag);
+ state_fio->FputInt32_BE(active_page);
+ state_fio->FputBool(sub_busy);
+ state_fio->FputBool(sub_run);
+ state_fio->FputBool(crt_flag);
+ state_fio->FputBool(vram_wrote);
+ state_fio->FputBool(is_cyclesteal);
+
+ state_fio->FputUint8(kanji1_addr.b.l);
+ state_fio->FputUint8(kanji1_addr.b.h);
+
+ state_fio->FputBool(do_attention);
+ state_fio->FputBool(irq_backup);
+ state_fio->FputBool(clock_fast);
+
#if defined(_FM77AV_VARIANTS)
- state_fio->FputBool(subcpu_resetreq);
- state_fio->FputBool(power_on_reset);
+ state_fio->FputBool(subcpu_resetreq);
+ state_fio->FputBool(power_on_reset);
#endif
- state_fio->FputBool(cancel_request);
- state_fio->FputBool(cancel_bak);
- state_fio->FputBool(key_firq_req);
+ state_fio->FputBool(cancel_request);
+ state_fio->FputBool(cancel_bak);
+ state_fio->FputBool(key_firq_req);
- state_fio->FputInt32(display_mode);
- state_fio->FputUint32(prev_clock);
-
- state_fio->Fwrite(dpalette_data, sizeof(dpalette_data), 1);
- state_fio->FputUint8(multimode_accessmask);
- state_fio->FputUint8(multimode_dispmask);
- state_fio->FputUint32(offset_point);
- for(i = 0; i < 2; i++) {
- state_fio->FputUint32(tmp_offset_point[i].d);
- state_fio->FputBool(offset_changed[i]);
- }
- state_fio->FputBool(offset_77av);
- state_fio->FputBool(diag_load_subrom_c);
+ state_fio->FputInt32_BE(display_mode);
+ state_fio->FputUint32_BE(prev_clock);
+ state_fio->Fwrite(dpalette_data, sizeof(dpalette_data), 1);
+ state_fio->FputUint8(multimode_accessmask);
+ state_fio->FputUint8(multimode_dispmask);
+ state_fio->FputUint32_BE(offset_point);
+ for(i = 0; i < 2; i++) {
+ state_fio->FputUint32_BE(tmp_offset_point[i].d);
+ state_fio->FputBool(offset_changed[i]);
+ }
+ state_fio->FputBool(offset_77av);
+ state_fio->FputBool(diag_load_subrom_c);
+
- state_fio->Fwrite(io_w_latch, sizeof(io_w_latch), 1);
- state_fio->Fwrite(console_ram, sizeof(console_ram), 1);
- state_fio->Fwrite(work_ram, sizeof(work_ram), 1);
- state_fio->Fwrite(shared_ram, sizeof(shared_ram), 1);
- state_fio->Fwrite(subsys_c, sizeof(subsys_c), 1);
- state_fio->Fwrite(gvram, sizeof(gvram), 1);
+ state_fio->Fwrite(io_w_latch, sizeof(io_w_latch), 1);
+ state_fio->Fwrite(console_ram, sizeof(console_ram), 1);
+ state_fio->Fwrite(work_ram, sizeof(work_ram), 1);
+ state_fio->Fwrite(shared_ram, sizeof(shared_ram), 1);
+ state_fio->Fwrite(subsys_c, sizeof(subsys_c), 1);
+ state_fio->Fwrite(gvram, sizeof(gvram), 1);
#if defined(_FM77L4)
- state_fio->FputBool(kanjisub);
- state_fio->FputBool(mode400line);
+ state_fio->FputBool(kanjisub);
+ state_fio->FputBool(mode400line);
#endif
#if defined(_FM77AV_VARIANTS)
- state_fio->FputBool(kanjisub);
+ state_fio->FputBool(kanjisub);
- state_fio->FputBool(vblank);
- state_fio->FputBool(vsync);
- state_fio->FputBool(hblank);
- state_fio->FputInt32(vblank_count);
- state_fio->FputUint32(displine);
-
- state_fio->FputBool(mode320);
- state_fio->FputInt32(display_page);
- state_fio->FputInt32(cgrom_bank);
+ state_fio->FputBool(vblank);
+ state_fio->FputBool(vsync);
+ state_fio->FputBool(hblank);
+ state_fio->FputInt32_BE(vblank_count);
+ state_fio->FputUint32_BE(displine);
+
+ state_fio->FputBool(mode320);
+ state_fio->FputInt32_BE(display_page);
+ state_fio->FputInt32_BE(cgrom_bank);
#if defined(_FM77AV40) || defined(_FM77AV40SX)|| defined(_FM77AV40SX)
- state_fio->FputInt32(vram_bank);
+ state_fio->FputInt32_BE(vram_bank);
#endif
- state_fio->FputInt32(offset_point_bank1);
+ state_fio->FputInt32_BE(offset_point_bank1);
- state_fio->FputUint8(subrom_bank);
- state_fio->FputUint8(subrom_bank_using);
+ state_fio->FputUint8(subrom_bank);
+ state_fio->FputUint8(subrom_bank_using);
- state_fio->FputBool(nmi_enable);
- state_fio->FputBool(use_alu);
-
- state_fio->FputUint8(apalette_index.b.l);
- state_fio->FputUint8(apalette_index.b.h);
+ state_fio->FputBool(nmi_enable);
+ state_fio->FputBool(use_alu);
+
+ state_fio->FputUint8(apalette_index.b.l);
+ state_fio->FputUint8(apalette_index.b.h);
- state_fio->Fwrite(analog_palette_r, sizeof(analog_palette_r), 1);
- state_fio->Fwrite(analog_palette_g, sizeof(analog_palette_g), 1);
- state_fio->Fwrite(analog_palette_b, sizeof(analog_palette_b), 1);
+ state_fio->Fwrite(analog_palette_r, sizeof(analog_palette_r), 1);
+ state_fio->Fwrite(analog_palette_g, sizeof(analog_palette_g), 1);
+ state_fio->Fwrite(analog_palette_b, sizeof(analog_palette_b), 1);
- state_fio->FputBool(diag_load_subrom_a);
- state_fio->FputBool(diag_load_subrom_b);
- state_fio->FputBool(diag_load_subrom_cg);
+ state_fio->FputBool(diag_load_subrom_a);
+ state_fio->FputBool(diag_load_subrom_b);
+ state_fio->FputBool(diag_load_subrom_cg);
- state_fio->Fwrite(subsys_a, sizeof(subsys_a), 1);
- state_fio->Fwrite(subsys_b, sizeof(subsys_b), 1);
- state_fio->Fwrite(subsys_cg, sizeof(subsys_cg), 1);
- state_fio->Fwrite(submem_hidden, sizeof(submem_hidden), 1);
+ state_fio->Fwrite(subsys_a, sizeof(subsys_a), 1);
+ state_fio->Fwrite(subsys_b, sizeof(subsys_b), 1);
+ state_fio->Fwrite(subsys_cg, sizeof(subsys_cg), 1);
+ state_fio->Fwrite(submem_hidden, sizeof(submem_hidden), 1);
# if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
- state_fio->FputBool(mode400line);
- state_fio->FputBool(mode256k);
-
- state_fio->FputBool(monitor_ram);
- state_fio->FputBool(monitor_ram_using);
-
- state_fio->FputUint16(window_low);
- state_fio->FputUint16(window_high);
- state_fio->FputUint16(window_xbegin);
- state_fio->FputUint16(window_xend);
- state_fio->FputBool(window_opened);
+ state_fio->FputBool(mode400line);
+ state_fio->FputBool(mode256k);
+
+ state_fio->FputBool(monitor_ram);
+ state_fio->FputBool(monitor_ram_using);
- state_fio->FputBool(kanji_level2);
- state_fio->FputUint8(kanji2_addr.b.l);
- state_fio->FputUint8(kanji2_addr.b.h);
-
- state_fio->FputUint8(vram_active_block);
- state_fio->FputUint8(vram_display_block);
- state_fio->FputUint8(monitor_ram_bank);
- state_fio->FputUint8(console_ram_bank);
- state_fio->FputBool(ram_protect);
+ state_fio->FputUint16_BE(window_low);
+ state_fio->FputUint16_BE(window_high);
+ state_fio->FputUint16_BE(window_xbegin);
+ state_fio->FputUint16_BE(window_xend);
+ state_fio->FputBool(window_opened);
- state_fio->FputUint32(cgram_bank);
- state_fio->Fwrite(subsys_ram, sizeof(subsys_ram), 1);
- state_fio->Fwrite(submem_cgram, sizeof(submem_cgram), 1);
- state_fio->Fwrite(submem_console_av40, sizeof(submem_console_av40), 1);
+ state_fio->FputBool(kanji_level2);
+ state_fio->FputUint8(kanji2_addr.b.l);
+ state_fio->FputUint8(kanji2_addr.b.h);
+
+ state_fio->FputUint8(vram_active_block);
+ state_fio->FputUint8(vram_display_block);
+ state_fio->FputUint8(monitor_ram_bank);
+ state_fio->FputUint8(console_ram_bank);
+ state_fio->FputBool(ram_protect);
+
+ state_fio->FputUint32_BE(cgram_bank);
+ state_fio->Fwrite(subsys_ram, sizeof(subsys_ram), 1);
+ state_fio->Fwrite(submem_cgram, sizeof(submem_cgram), 1);
+ state_fio->Fwrite(submem_console_av40, sizeof(submem_console_av40), 1);
# endif
#endif
+ }
// V2
+ {
+ state_fio->FputInt32_BE(nmi_event_id);
+#if defined(_FM77AV_VARIANTS)
+ state_fio->FputInt32_BE(hblank_event_id);
+ state_fio->FputInt32_BE(hdisp_event_id);
+ state_fio->FputInt32_BE(vsync_event_id);
+ state_fio->FputInt32_BE(vstart_event_id);
+#endif
+ }
}
bool DISPLAY::load_state(FILEIO *state_fio)
{
- uint32 version = state_fio->FgetUint32();
+ uint32 version = state_fio->FgetUint32_BE();
int addr;
int i;
- if(this_device_id != state_fio->FgetInt32()) return false;
+ if(this_device_id != state_fio->FgetInt32_BE()) return false;
if(version >= 1) {
- clr_count = state_fio->FgetInt32();
+ clr_count = state_fio->FgetInt32_BE();
halt_flag = state_fio->FgetBool();
- active_page = state_fio->FgetInt32();
+ active_page = state_fio->FgetInt32_BE();
sub_busy = state_fio->FgetBool();
sub_run = state_fio->FgetBool();
crt_flag = state_fio->FgetBool();
cancel_bak = state_fio->FgetBool();
key_firq_req = state_fio->FgetBool();
- display_mode = state_fio->FgetInt32();
- prev_clock = state_fio->FgetUint32();
+ display_mode = state_fio->FgetInt32_BE();
+ prev_clock = state_fio->FgetUint32_BE();
state_fio->Fread(dpalette_data, sizeof(dpalette_data), 1);
for(addr = 0; addr < 8; addr++) set_dpalette(addr, dpalette_data[addr]);
multimode_accessmask = state_fio->FgetUint8();
multimode_dispmask = state_fio->FgetUint8();
- offset_point = state_fio->FgetUint32();
+ offset_point = state_fio->FgetUint32_BE();
for(i = 0; i < 2; i++) {
- tmp_offset_point[i].d = state_fio->FgetUint32();
+ tmp_offset_point[i].d = state_fio->FgetUint32_BE();
offset_changed[i] = state_fio->FgetBool();
}
offset_77av = state_fio->FgetBool();
vblank = state_fio->FgetBool();
vsync = state_fio->FgetBool();
hblank = state_fio->FgetBool();
- vblank_count = state_fio->FgetInt32();
- displine = state_fio->FgetUint32();
+ vblank_count = state_fio->FgetInt32_BE();
+ displine = state_fio->FgetUint32_BE();
mode320 = state_fio->FgetBool();
- display_page = state_fio->FgetInt32();
- cgrom_bank = state_fio->FgetInt32();
+ display_page = state_fio->FgetInt32_BE();
+ cgrom_bank = state_fio->FgetInt32_BE();
#if defined(_FM77AV40) || defined(_FM77AV40SX)|| defined(_FM77AV40SX)
- vram_bank = state_fio->FgetInt32();
+ vram_bank = state_fio->FgetInt32_BE();
#endif
- offset_point_bank1 = state_fio->FgetInt32();
+ offset_point_bank1 = state_fio->FgetInt32_BE();
subrom_bank = state_fio->FgetUint8();
subrom_bank_using = state_fio->FgetUint8();
monitor_ram = state_fio->FgetBool();
monitor_ram_using = state_fio->FgetBool();
- window_low = state_fio->FgetUint16();
- window_high = state_fio->FgetUint16();
- window_xbegin = state_fio->FgetUint16();
- window_xend = state_fio->FgetUint16();
+ window_low = state_fio->FgetUint16_BE();
+ window_high = state_fio->FgetUint16_BE();
+ window_xbegin = state_fio->FgetUint16_BE();
+ window_xend = state_fio->FgetUint16_BE();
window_opened = state_fio->FgetBool();
kanji_level2 = state_fio->FgetBool();
console_ram_bank = state_fio->FgetUint8();
ram_protect = state_fio->FgetBool();
- cgram_bank = state_fio->FgetUint32();
+cgram_bank = state_fio->FgetUint32_BE();
state_fio->Fread(subsys_ram, sizeof(subsys_ram), 1);
state_fio->Fread(submem_cgram, sizeof(submem_cgram), 1);
state_fio->Fread(submem_console_av40, sizeof(submem_console_av40), 1);
#endif
if(version == 1) return true;
}
- //V2
- return false;
+ if(version >= 2) { //V2
+ nmi_event_id = state_fio->FgetInt32_BE();
+#if defined(_FM77AV_VARIANTS)
+ hblank_event_id = state_fio->FgetInt32_BE();
+ hdisp_event_id = state_fio->FgetInt32_BE();
+ vsync_event_id = state_fio->FgetInt32_BE();
+ vstart_event_id = state_fio->FgetInt32_BE();
+#endif
+ }
+ return true;
}
event = new EVENT(this, emu); // must be 2nd device
dummycpu = new DEVICE(this, emu);
+ // basic devices
kanjiclass1 = new KANJIROM(this, emu, false);
#ifdef CAPABLE_KANJI_CLASS2
kanjiclass2 = new KANJIROM(this, emu, true);
// I/Os
drec = new DATAREC(this, emu);
pcm1bit = new PCM1BIT(this, emu);
-// beep = new BEEP(this, emu);
fdc = new MB8877(this, emu);
opn[0] = new YM2203(this, emu); // OPN
#if !defined(_FM77AV_VARIANTS)
psg = new YM2203(this, emu);
#endif
- display = new DISPLAY(this, emu);
- mainio = new FM7_MAINIO(this, emu);
- mainmem = new FM7_MAINMEM(this, emu);
keyboard = new KEYBOARD(this, emu);
#if defined(_FM77AV_VARIANTS)
alu = new MB61VH010(this, emu);
#endif
-
- // basic devices
+ display = new DISPLAY(this, emu);
+ mainmem = new FM7_MAINMEM(this, emu);
+ mainio = new FM7_MAINIO(this, emu);
+
+ maincpu = new MC6809(this, emu);
subcpu = new MC6809(this, emu);
#ifdef WITH_Z80
z80cpu = new Z80(this, emu);
#endif
- maincpu = new MC6809(this, emu);
+#ifdef USE_DEBUGGER
+ maincpu->set_context_debugger(new DEBUGGER(this, emu));
+ subcpu->set_context_debugger(new DEBUGGER(this, emu));
+#endif
+ for(DEVICE* device = first_device; device; device = device->next_device) {
+ device->initialize();
+ }
connect_bus();
initialize();
}
}
#endif
#if defined(_FM77AV40) || defined(_FM77AV20)
- event->set_context_cpu(maincpu, MAINCLOCK_FAST_MMR);
+ event->set_context_cpu(maincpu, mainclock);
#else
- event->set_context_cpu(maincpu, MAINCLOCK_NORMAL);
+ event->set_context_cpu(maincpu, mainclock);
#endif
- event->set_context_cpu(subcpu, SUBCLOCK_NORMAL);
+ event->set_context_cpu(subcpu, subclock);
#ifdef WITH_Z80
event->set_context_cpu(z80cpu, 4000000);
event->set_context_sound(opn[1]);
event->set_context_sound(opn[2]);
event->set_context_sound(drec);
- //event->register_vline_event(display);
+
event->register_frame_event(display);
- //event->register_vline_event(mainio);
+ event->register_vline_event(display);
+ event->register_vline_event(mainio);
mainio->set_context_maincpu(maincpu);
mainio->set_context_subcpu(subcpu);
fdc->set_context_drq(mainio, FM7_MAINIO_FDC_DRQ, 0x1);
// SOUND
mainio->set_context_beep(pcm1bit);
- //mainio->set_context_beep(beep);
opn[0]->set_context_irq(mainio, FM7_MAINIO_OPN_IRQ, 0xffffffff);
mainio->set_context_opn(opn[0], 0);
maincpu->set_context_mem(mainmem);
subcpu->set_context_mem(display);
-#ifdef USE_DEBUGGER
- maincpu->set_context_debugger(new DEBUGGER(this, emu));
- subcpu->set_context_debugger(new DEBUGGER(this, emu));
-#endif
event->register_frame_event(joystick);
- for(DEVICE* device = first_device; device; device = device->next_device) {
- device->initialize();
- }
- //maincpu->write_signal(SIG_CPU_BUSREQ, 1, 1);
- //subcpu->write_signal(SIG_CPU_BUSREQ, 1, 1);
-
+
for(int i = 0; i < 2; i++) {
#if defined(_FM77AV20) || defined(_FM77AV40SX) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
fdc->set_drive_type(i, DRIVE_TYPE_2DD);
for(DEVICE* device = first_device; device; device = device->next_device) {
device->reset();
}
+ //subcpu->reset();
+ //maincpu->reset();
+
opn[0]->SetReg(0x2e, 0); // set prescaler
opn[1]->SetReg(0x2e, 0); // set prescaler
opn[2]->SetReg(0x2e, 0); // set prescaler
};
enum {
- FM7_MAINIO_IS_BASICROM = 0x100000,
+ FM7_MAINIO_IS_BASICROM = 0x200000,
FM7_MAINIO_BOOTMODE,
+ FM7_MAINIO_BOOTRAM_RW,
FM7_MAINIO_READ_FD0F,
+ FM7_MAINIO_PUSH_FD0F,
FM7_MAINIO_CLOCKMODE,
FM7_MAINIO_INITROM_ENABLED,
FM7_MAINIO_EXTBANK,
FM7_MAINIO_WINDOW_ENABLED,
FM7_MAINIO_WINDOW_OFFSET,
FM7_MAINIO_MMR_SEGMENT,
- FM7_MAINIO_MMR_BANK = 0x100080,
+ FM7_MAINIO_MMR_BANK = 0x200100,
};
enum {
#include <SDL2/SDL.h>
#endif
+FM7_MAINIO::FM7_MAINIO(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
+{
+ int i;
+ p_vm = parent_vm;
+ p_emu = parent_emu;
+ kanjiclass1 = NULL;
+ kanjiclass2 = NULL;
+ opn_psg_77av = false;
+ // FD00
+ clock_fast = true;
+ lpt_strobe = false;
+ lpt_slctin = false;
+ // FD01
+ lpt_outdata = 0x00;
+ // FD02
+ cmt_indat = false; // bit7
+ cmt_invert = false; // Invert signal
+ lpt_det2 = false;
+ lpt_det1 = false;
+ lpt_pe = false;
+ lpt_ackng_inv = false;
+ lpt_error_inv = false;
+ lpt_busy = false;
+ // FD04
+ stat_fdmode_2hd = false; // R/W : bit6, '0' = 2HD, '1' = 2DD. FM-77 Only.
+ stat_kanjirom = true; // R/W : bit5, '0' = sub, '1' = main. FM-77 Only.
+ stat_400linecard = false;// R/W : bit4, '0' = connected. FM-77 Only.
+ stat_400linemode = false; // R/W : bit3, '0' = 400line, '1' = 200line.
+ firq_break_key = false; // bit1, ON = '0'.
+ firq_sub_attention = false; // bit0, ON = '0'.
+ intmode_fdc = false; // bit2, '0' = normal, '1' = SFD.
+ // FD05
+ extdet_neg = false;
+#ifdef WITH_Z80
+ z80_sel = false; // bit0 : '1' = Z80. Maybe only FM-7/77.
+#endif
+ // FD06,07
+ intstat_syndet = false;
+ intstat_rxrdy = false;
+ intstat_txrdy = false;
+ // FD0B
+ bootmode = 0x00;
+ // FD0D
+ // FD0F
+ stat_romrammode = true; // ROM ON
+
+ // FD15/ FD46 / FD51
+ connect_opn = false;
+ connect_whg = false;
+ connect_thg = false;
+
+ for(i = 0; i < 3; i++) {
+ opn_address[i] = 0x00;
+ opn_data[i] = 0x00;
+ opn_cmdreg[i] = 0;
+ }
+ joyport_a = 0x00;
+ joyport_b = 0x00;
+
+ intstat_whg = false;
+ intstat_thg = false;
+ // FD17
+ intstat_opn = false;
+ intstat_mouse = false;
+ mouse_enable = false;
+ // FD18-FD1F
+ connect_fdc = false;
+ fdc_statreg = 0x00;
+ fdc_cmdreg = 0x00;
+ fdc_trackreg = 0x00;
+ fdc_sectreg = 0x00;
+ fdc_datareg = 0x00;
+ fdc_headreg = 0x00;
+ fdc_drvsel = 0x00;
+ fdc_motor = false;
+ irqstat_fdc = 0;
+ // FD20, FD21, FD22, FD23
+ connect_kanjiroml1 = false;
+#if defined(_FM77AV_VARIANTS)
+ enable_initiator = true;
+ // FD2C, FD2D, FD2E, FD2F
+ connect_kanjiroml2 = false;
+#endif
+#if defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
+ boot_ram = false;
+#endif
+ memset(io_w_latch, 0x00, 0x100);
+}
+
+FM7_MAINIO::~FM7_MAINIO()
+{
+}
+
+
+
void FM7_MAINIO::initialize()
{
int i;
# endif
# endif
#endif
+#if defined(_FM77AV_VARIANTS)
+ enable_initiator = true;
+#endif
+#ifdef HAS_MMR
+ mmr_enabled = false;
+ mmr_fast = false;
+ window_enabled = false;
+ mmr_segment = 0x00;
+ window_offset = 0x0000;
+ for(i = 0x00; i < 0x80; i++) {
+ mmr_table[i] = 0;
+ }
+#endif
}
void FM7_MAINIO::reset()
if(event_beep < 0) register_event(this, EVENT_BEEP_CYCLE, (1000.0 * 1000.0) / (1200.0 * 2.0), true, &event_beep);
bootmode = config.boot_mode & 3;
+ mainmem->write_signal(FM7_MAINIO_IS_BASICROM, (bootmode == 0) ? 0xffffffff : 0, 0xffffffff);
#if defined(_FM77AV_VARIANTS)
opn_psg_77av = true;
hotreset = false;
connect_whg = false;
#if defined(_FM77_VARIANTS)
boot_ram = false;
-#endif
+ mainmem->write_signal(FM7_MAINIO_BOOTRAM_RW, 0 , 0xffffffff);
+#endif
#if defined(_FM77AV_VARIANTS)
enable_initiator = true;
+ mainmem->write_signal(FM7_MAINIO_INITROM_ENABLED, (enable_initiator) ? 0xffffffff : 0 , 0xffffffff);
boot_ram = true;
-#endif
-#ifdef HAS_MMR
- for(i = 0x00; i < 0x80; i++) mmr_table[i] = 0;
+ //boot_ram = false;
+ mainmem->write_signal(FM7_MAINIO_BOOTRAM_RW, boot_ram ? 0xffffffff : 0 , 0xffffffff);
#endif
// FD05
extdet_neg = false;
extdet_neg = false;
stat_romrammode = true;
- bootmode = config.boot_mode & 3;
if(bootmode == 0) { // IF BASIC BOOT THEN ROM
stat_romrammode = true;
} else { // ELSE RAM
stat_romrammode = false;
}
+ mainmem->write_signal(FM7_MAINIO_PUSH_FD0F, (stat_romrammode) ? 0xffffffff : 0, 0xffffffff);
#if defined(_FM77AV_VARIANTS)
- boot_ram = false;
kaddress.d = 0;
#elif defined(_FM77_VARIANTS)
kaddress.d = 0;
#endif
#if defined(_FM77AV_VARIANTS)
- //sub_monitor_type = display->read_signal(SIG_FM7_SUB_BANK);
sub_monitor_type = 0x00;
- enable_initiator = true;
- boot_ram = true;
#endif
#ifdef HAS_MMR
window_enabled = false;
mmr_segment = 0x00;
window_offset = 0x0000;
+ mainmem->write_signal(FM7_MAINIO_WINDOW_ENABLED, (window_enabled) ? 0xffffffff : 0, 0xffffffff);
+ mainmem->write_data8(FM7_MAINIO_WINDOW_OFFSET, window_offset);
+ mainmem->write_signal(FM7_MAINIO_FASTMMR_ENABLED, (mmr_fast) ? 0xffffffff : 0, 0xffffffff);
+ mainmem->write_signal(FM7_MAINIO_MMR_ENABLED, (mmr_enabled) ? 0xffffffff : 0, 0xffffffff);
+ mainmem->write_data8(FM7_MAINIO_MMR_SEGMENT, mmr_segment);
+#endif
+#ifdef HAS_MMR
+ for(i = 0x00; i < 0x80; i++) {
+ mmr_table[i] = 0;
+ mainmem->write_data8(FM7_MAINIO_MMR_BANK + i, (uint32)mmr_table[i]);
+ }
#endif
switch(config.cpu_type){
case 0:
break;
}
this->write_signal(FM7_MAINIO_CLOCKMODE, clock_fast ? 1 : 0, 1);
+ mainmem->write_signal(FM7_MAINIO_CLOCKMODE, clock_fast ? 1 : 0, 1);
// FD03
irqmask_syndet = true;
memset(io_w_latch, 0x00, 0x100);
//mainmem->reset();
- maincpu->reset();
+ //maincpu->reset();
}
}
if(f != clock_fast) {
this->write_signal(FM7_MAINIO_CLOCKMODE, clock_fast ? 1 : 0, 1);
+ mainmem->write_signal(FM7_MAINIO_CLOCKMODE, clock_fast ? 1 : 0, 1);
}
}
extdet_neg = flag;
}
+void FM7_MAINIO::write_fd0f(void)
+{
+ stat_romrammode = false;
+ mainmem->write_signal(FM7_MAINIO_PUSH_FD0F, 0, 0xffffffff);
+}
+uint8 FM7_MAINIO::read_fd0f(void)
+{
+ stat_romrammode = true;
+ mainmem->write_signal(FM7_MAINIO_PUSH_FD0F, 0xffffffff, 0xffffffff);
+ return 0xff;
+}
+
+bool FM7_MAINIO::get_rommode_fd0f(void)
+{
+ return stat_romrammode;
+}
+
+
// Kanji ROM, FD20 AND FD21 (or SUBSYSTEM)
void FM7_MAINIO::write_kanjiaddr_hi(uint8 addr)
{
clock_fast = false;
}
{
- uint32 clocks;
+ uint32 clocks = 1794000;
#if defined(_FM77AV_VARIANTS) || defined(_FM77_VARIANTS)
if(mmr_enabled) {
if(mmr_fast) {
#endif
+uint32 FM7_MAINIO::read_io8(uint32 addr)
+{ // This is only for debug.
+ addr = addr & 0xfff;
+ if(addr < 0x100) {
+ return io_w_latch[addr];
+ } else if(addr < 0x500) {
+ uint32 ofset = addr & 0xff;
+ uint opnbank = (addr - 0x100) >> 8;
+ return opn_regs[opnbank][ofset];
+ } else if(addr < 0x600) {
+#if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX)
+ return mmr_table[addr & 0xff];
+#elif defined(_FM77AV_VARIANTS) || defined(_FM77_VARIANTS)
+ return mmr_table[addr & 0x3f];
+#else
+ return 0xff;
+#endif
+ }
+ return 0xff;
+}
+
+
uint32 FM7_MAINIO::read_data8(uint32 addr)
{
uint32 retval;
}
// Another:
return retval;
- } else if(addr == FM7_MAINIO_READ_FD0F) {
- if(stat_romrammode) return 0xffffffff;
- return 0;
} else if(addr == FM7_MAINIO_CLOCKMODE) {
return (uint32)get_clockmode();
}
-#if defined(HAS_MMR)
- else if(addr == FM7_MAINIO_MMR_ENABLED) {
- retval = (mmr_enabled) ? 0xffffffff:0x00000000;
- return retval;
- } else if(addr == FM7_MAINIO_WINDOW_ENABLED) {
- retval = (window_enabled) ? 0xffffffff:0x00000000;
- return retval;
- } else if(addr == FM7_MAINIO_WINDOW_OFFSET) {
- retval = (uint32)window_offset;
- return retval;
- } else if(addr == FM7_MAINIO_MMR_SEGMENT) {
- retval = (uint32) mmr_segment;
- return retval;
- } else if((addr >= FM7_MAINIO_MMR_BANK) && (addr < (FM7_MAINIO_MMR_BANK + 16))) {
-#if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX)
- retval = mmr_table[(addr - FM7_MAINIO_MMR_BANK) | (mmr_segment << 4)];
-#else
- retval = mmr_table[(addr - FM7_MAINIO_MMR_BANK) | (mmr_segment << 4)] & 0x3f;
-#endif
- return retval;
- }
-#endif
- else if(addr == FM7_MAINIO_IS_BASICROM) {
- retval = 0;
- if(bootmode == 0) retval = 0xffffffff;
- return retval;
- } else if(addr == FM7_MAINIO_BOOTMODE) {
- retval = bootmode & 0x03;
-#if defined(_FM77) || defined(_FM77L2) || defined(_FM77L4) || defined(_FM77AV_VARIANTS)
- if(boot_ram) retval = 4;
-#endif
- return retval;
- }
#if defined(_FM77AV_VARIANTS)
- else if(addr == FM7_MAINIO_INITROM_ENABLED) {
- retval = (enable_initiator) ? 0xffffffff : 0x00000000;
- return retval;
- } else if(addr == FM7_MAINIO_SUBMONITOR_ROM) {
+ else if(addr == FM7_MAINIO_SUBMONITOR_ROM) {
retval = sub_monitor_type & 0x03;
return retval;
} else if(addr == FM7_MAINIO_SUBMONITOR_RAM) {
addr = addr & 0xff;
io_w_latch[addr] = data;
#if defined(HAS_MMR)
- if((addr < 0x90) && (addr >= 0x80)) {
+ if((addr < 0x90) && (addr >= 0x80)) {
#if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX)
mmr_table[addr - 0x80 + mmr_segment * 16] = data;
+ mainmem->write_data8(FM7_MAINIO_MMR_BANK + mmr_segment * 16 + addr - 0x80, data);
#else
mmr_table[addr - 0x80 + (mmr_segment & 0x03) * 16] = data & 0x3f;
+ mainmem->write_data8(FM7_MAINIO_MMR_BANK + (mmr_segment & 0x03) * 16 + addr - 0x80, data & 0x3f);
#endif
return;
}
flag = enable_initiator;
//printf("INITIATOR ENABLE = %02x\n", data);
enable_initiator = ((data & 0x02) == 0) ? true : false;
- //if(flag != enable_initiator) {
- //maincpu->reset();
- //}
+ mainmem->write_signal(FM7_MAINIO_INITROM_ENABLED, (enable_initiator) ? 0xffffffff : 0 , 0xffffffff);
break;
case 0x12:
display->write_signal(SIG_DISPLAY_MODE320, data, 0x40);
// printf("MMR SEGMENT: %02x\n", data & 3);
mmr_segment = data & 3;
#endif
+ mainmem->write_data8(FM7_MAINIO_MMR_SEGMENT, (uint32)mmr_segment);
break;
case 0x92:
window_offset = data & 0x00ff;
+ mainmem->write_data8(FM7_MAINIO_WINDOW_OFFSET, (uint32)window_offset);
break;
case 0x93:
if((data & 0x01) == 0) {
boot_ram = false;
} else {
boot_ram = true;
- }
+ }
+ mainmem->write_signal(FM7_MAINIO_BOOTRAM_RW, (boot_ram) ? 0xffffffff : 0 , 0xffffffff);
+ mainmem->write_signal(FM7_MAINIO_BOOTMODE, bootmode, 7);
+ mainmem->write_signal(FM7_MAINIO_IS_BASICROM, (bootmode == 0) ? 0xffffffff : 0, 0xffffffff);
if((data & 0x40) == 0) {
window_enabled = false;
} else {
window_enabled = true;
}
+ mainmem->write_signal(FM7_MAINIO_WINDOW_ENABLED, window_enabled ? 1 : 0, 1);
flag = mmr_enabled;
if((data & 0x80) == 0) {
mmr_enabled = false;
}
if(flag != mmr_enabled) {
this->write_signal(FM7_MAINIO_CLOCKMODE, clock_fast ? 1 : 0, 1);
+ mainmem->write_signal(FM7_MAINIO_CLOCKMODE, clock_fast ? 1 : 0, 1);
+ mainmem->write_signal(FM7_MAINIO_MMR_ENABLED, mmr_enabled ? 1 : 0, 1);
}
break;
#endif
return;
} else if(addr == FM7_MAINIO_BOOTMODE) {
bootmode = data & 0x03;
+ mainmem->write_signal(FM7_MAINIO_IS_BASICROM, (bootmode == 0) ? 0xffffffff : 0, 0xffffffff);
+ mainmem->write_signal(FM7_MAINIO_BOOTMODE, bootmode, 0x03);
+ mainmem->write_signal(FM7_MAINIO_BOOTRAM_RW, (boot_ram) ? 0xffffffff : 0 , 0xffffffff);
return;
} else if(addr == FM7_MAINIO_CLOCKMODE) {
set_clockmode((uint8)data);
break;
}
this->write_signal(FM7_MAINIO_CLOCKMODE, clock_fast ? 1 : 0, 1);
+ mainmem->write_signal(FM7_MAINIO_CLOCKMODE, clock_fast ? 1 : 0, 1);
}
void FM7_MAINIO::event_vline(int v, int clock)
{
}
-#define STATE_VERSION 1
+#define STATE_VERSION 2
void FM7_MAINIO::save_state(FILEIO *state_fio)
{
int ch;
int addr;
- state_fio->FputUint32(STATE_VERSION);
- state_fio->FputInt32(this_device_id);
+ state_fio->FputUint32_BE(STATE_VERSION);
+ state_fio->FputInt32_BE(this_device_id);
// Version 1
- for(addr = 0; addr < 0x100; addr++) state_fio->FputUint8(io_w_latch[addr]);
- // FD00
- state_fio->FputBool(clock_fast);
- state_fio->FputBool(lpt_strobe);
- state_fio->FputBool(lpt_slctin);
- state_fio->FputBool(beep_flag);
- state_fio->FputBool(beep_snd);
+ {
+ for(addr = 0; addr < 0x100; addr++) state_fio->FputUint8(io_w_latch[addr]);
+ // FD00
+ state_fio->FputBool(clock_fast);
+ state_fio->FputBool(lpt_strobe);
+ state_fio->FputBool(lpt_slctin);
+ state_fio->FputBool(beep_flag);
+ state_fio->FputBool(beep_snd);
- // FD01
- state_fio->FputUint8(lpt_outdata);
- // FD02
- state_fio->FputBool(cmt_indat);
- state_fio->FputBool(cmt_invert);
- state_fio->FputBool(lpt_det2);
- state_fio->FputBool(lpt_det1);
- state_fio->FputBool(lpt_pe);
- state_fio->FputBool(lpt_ackng_inv);
- state_fio->FputBool(lpt_error_inv);
- state_fio->FputUint8(irqmask_reg0);
-
- state_fio->FputBool(irqmask_syndet);
- state_fio->FputBool(irqmask_rxrdy);
- state_fio->FputBool(irqmask_txrdy);
- state_fio->FputBool(irqmask_mfd);
- state_fio->FputBool(irqmask_timer);
- state_fio->FputBool(irqmask_printer);
- state_fio->FputBool(irqmask_keyboard);
-
- // FD03
- state_fio->FputUint8(irqstat_reg0);
+ // FD01
+ state_fio->FputUint8(lpt_outdata);
+ // FD02
+ state_fio->FputBool(cmt_indat);
+ state_fio->FputBool(cmt_invert);
+ state_fio->FputBool(lpt_det2);
+ state_fio->FputBool(lpt_det1);
+ state_fio->FputBool(lpt_pe);
+ state_fio->FputBool(lpt_ackng_inv);
+ state_fio->FputBool(lpt_error_inv);
+ state_fio->FputUint8(irqmask_reg0);
+
+ state_fio->FputBool(irqmask_syndet);
+ state_fio->FputBool(irqmask_rxrdy);
+ state_fio->FputBool(irqmask_txrdy);
+ state_fio->FputBool(irqmask_mfd);
+ state_fio->FputBool(irqmask_timer);
+ state_fio->FputBool(irqmask_printer);
+ state_fio->FputBool(irqmask_keyboard);
- state_fio->FputBool(irqstat_timer);
- state_fio->FputBool(irqstat_printer);
- state_fio->FputBool(irqstat_keyboard);
-
- // FD04
+ // FD03
+ state_fio->FputUint8(irqstat_reg0);
+
+ state_fio->FputBool(irqstat_timer);
+ state_fio->FputBool(irqstat_printer);
+ state_fio->FputBool(irqstat_keyboard);
+
+ // FD04
#if defined(_FM77_VARIANTS)
- state_fio->FputBool(stat_fdmode_2hd);
- state_fio->FputBool(stat_kanjirom);
- state_fio->FputBool(stat_400linecard);
+ state_fio->FputBool(stat_fdmode_2hd);
+ state_fio->FputBool(stat_kanjirom);
+ state_fio->FputBool(stat_400linecard);
#endif
- state_fio->FputBool(firq_break_key);
- state_fio->FputBool(firq_sub_attention);
-
- state_fio->FputBool(intmode_fdc);
- // FD05
- state_fio->FputBool(extdet_neg);
- //state_fio->FputBool(sub_busy);
- state_fio->FputBool(sub_halt);
- //state_fio->FputBool(sub_halt_bak);
- state_fio->FputBool(sub_cancel);
- //state_fio->FputBool(sub_cancel_bak);
+ state_fio->FputBool(firq_break_key);
+ state_fio->FputBool(firq_sub_attention);
+
+ state_fio->FputBool(intmode_fdc);
+ // FD05
+ state_fio->FputBool(extdet_neg);
+ //state_fio->FputBool(sub_busy);
+ state_fio->FputBool(sub_halt);
+ //state_fio->FputBool(sub_halt_bak);
+ state_fio->FputBool(sub_cancel);
+ //state_fio->FputBool(sub_cancel_bak);
#if defined(WITH_Z80)
- state_fio->FputBool(z80_sel);
+ state_fio->FputBool(z80_sel);
#endif
- // FD06, 07
- state_fio->FputBool(intstat_syndet);
- state_fio->FputBool(intstat_rxrdy);
- state_fio->FputBool(intstat_txrdy);
+ // FD06, 07
+ state_fio->FputBool(intstat_syndet);
+ state_fio->FputBool(intstat_rxrdy);
+ state_fio->FputBool(intstat_txrdy);
// FD0B
- state_fio->FputUint32(bootmode);
+ state_fio->FputUint32_BE(bootmode);
// FD0F
- state_fio->FputBool(stat_romrammode);
+ state_fio->FputBool(stat_romrammode);
- state_fio->FputBool(connect_opn);
- state_fio->FputBool(connect_whg);
- state_fio->FputBool(connect_thg);
-
- state_fio->FputBool(opn_psg_77av);
+ state_fio->FputBool(connect_opn);
+ state_fio->FputBool(connect_whg);
+ state_fio->FputBool(connect_thg);
+
+ state_fio->FputBool(opn_psg_77av);
- for(ch = 0; ch < 4; ch++) {
- state_fio->FputUint32(opn_address[ch]);
- state_fio->FputUint32(opn_data[ch]);
- state_fio->FputUint32(opn_stat[ch]);
- state_fio->FputUint32(opn_cmdreg[ch]);
- state_fio->FputUint32(opn_ch3mode[ch]);
- }
- state_fio->FputUint32(joyport_a);
- state_fio->FputUint32(joyport_b);
+ for(ch = 0; ch < 4; ch++) {
+ state_fio->FputUint32_BE(opn_address[ch]);
+ state_fio->FputUint32_BE(opn_data[ch]);
+ state_fio->FputUint32_BE(opn_stat[ch]);
+ state_fio->FputUint32_BE(opn_cmdreg[ch]);
+ state_fio->FputUint32_BE(opn_ch3mode[ch]);
+ }
+ state_fio->FputUint32_BE(joyport_a);
+ state_fio->FputUint32_BE(joyport_b);
- state_fio->FputBool(intstat_opn);
- state_fio->FputBool(intstat_mouse);
- state_fio->FputBool(mouse_enable);
+ state_fio->FputBool(intstat_opn);
+ state_fio->FputBool(intstat_mouse);
+ state_fio->FputBool(mouse_enable);
- state_fio->FputBool(intstat_whg);
- state_fio->FputBool(intstat_thg);
+ state_fio->FputBool(intstat_whg);
+ state_fio->FputBool(intstat_thg);
// FDC
- state_fio->FputBool(connect_fdc);
- state_fio->FputUint8(fdc_statreg);
- state_fio->FputUint8(fdc_cmdreg);
- state_fio->FputUint8(fdc_trackreg);
- state_fio->FputUint8(fdc_sectreg);
- state_fio->FputUint8(fdc_datareg);
- state_fio->FputUint8(fdc_headreg);
- state_fio->FputUint8(fdc_drvsel);
- state_fio->FputUint8(irqreg_fdc);
- state_fio->FputBool(fdc_motor);
- state_fio->FputBool(irqstat_fdc);
-
- // KANJI ROM
- state_fio->FputBool(connect_kanjiroml1);
- state_fio->FputUint8(kaddress.b.l);
- state_fio->FputUint8(kaddress.b.h);
+ state_fio->FputBool(connect_fdc);
+ state_fio->FputUint8(fdc_statreg);
+ state_fio->FputUint8(fdc_cmdreg);
+ state_fio->FputUint8(fdc_trackreg);
+ state_fio->FputUint8(fdc_sectreg);
+ state_fio->FputUint8(fdc_datareg);
+ state_fio->FputUint8(fdc_headreg);
+ state_fio->FputUint8(fdc_drvsel);
+ state_fio->FputUint8(irqreg_fdc);
+ state_fio->FputBool(fdc_motor);
+ state_fio->FputBool(irqstat_fdc);
+
+ // KANJI ROM
+ state_fio->FputBool(connect_kanjiroml1);
+ state_fio->FputUint8(kaddress.b.l);
+ state_fio->FputUint8(kaddress.b.h);
#if defined(_FM77AV_VARIANTS)
- state_fio->FputBool(connect_kanjiroml2);
- state_fio->FputUint8(kaddress_l2.b.l);
- state_fio->FputUint8(kaddress_l2.b.h);
+ state_fio->FputBool(connect_kanjiroml2);
+ state_fio->FputUint8(kaddress_l2.b.l);
+ state_fio->FputUint8(kaddress_l2.b.h);
- state_fio->FputBool(boot_ram);
- state_fio->FputBool(enable_initiator);
- state_fio->FputBool(hotreset);
- // FD13
- state_fio->FputUint8(sub_monitor_type);
- //state_fio->FputUint8(sub_monitor_bak);
+ state_fio->FputBool(boot_ram);
+ state_fio->FputBool(enable_initiator);
+ state_fio->FputBool(hotreset);
+ // FD13
+ state_fio->FputUint8(sub_monitor_type);
+ //state_fio->FputUint8(sub_monitor_bak);
#endif
- // MMR
+ // MMR
#if defined(HAS_MMR)
- state_fio->FputBool(mmr_enabled);
- state_fio->FputBool(mmr_fast);
- state_fio->FputBool(window_enabled);
- state_fio->FputUint8(mmr_segment);
- for(addr = 0; addr < 0x80; addr++) state_fio->FputUint8(mmr_table[addr]);
- state_fio->FputUint32(window_offset);
+ state_fio->FputBool(mmr_enabled);
+ state_fio->FputBool(mmr_fast);
+ state_fio->FputBool(window_enabled);
+ state_fio->FputUint8(mmr_segment);
+ for(addr = 0; addr < 0x80; addr++) state_fio->FputUint8(mmr_table[addr]);
+ state_fio->FputUint32_BE(window_offset);
#endif
- // V2
+ }
+ //V2
+ {
+ state_fio->FputInt32_BE(event_beep);
+ state_fio->FputInt32_BE(event_beep_oneshot);
+ state_fio->FputInt32_BE(event_timerirq);
+ }
}
bool FM7_MAINIO::load_state(FILEIO *state_fio)
bool stat = false;
uint32 version;
- version = state_fio->FgetUint32();
- if(this_device_id != state_fio->FgetInt32()) return false;
+ version = state_fio->FgetUint32_BE();
+ if(this_device_id != state_fio->FgetInt32_BE()) return false;
if(version >= 1) {
for(addr = 0; addr < 0x100; addr++) io_w_latch[addr] = state_fio->FgetUint8();
intstat_txrdy = state_fio->FgetBool();
// FD0B
- bootmode = state_fio->FgetUint32();
+ bootmode = state_fio->FgetUint32_BE();
// FD0F
stat_romrammode = state_fio->FgetBool();
connect_opn = state_fio->FgetBool();
opn_psg_77av = state_fio->FgetBool();
for(ch = 0; ch < 4; ch++) {
- opn_address[ch] = state_fio->FgetUint32();
- opn_data[ch] = state_fio->FgetUint32();
- opn_stat[ch] = state_fio->FgetUint32();
- opn_cmdreg[ch] = state_fio->FgetUint32();
- opn_ch3mode[ch] = state_fio->FgetUint32();
+ opn_address[ch] = state_fio->FgetUint32_BE();
+ opn_data[ch] = state_fio->FgetUint32_BE();
+ opn_stat[ch] = state_fio->FgetUint32_BE();
+ opn_cmdreg[ch] = state_fio->FgetUint32_BE();
+ opn_ch3mode[ch] = state_fio->FgetUint32_BE();
}
- joyport_a = state_fio->FgetUint32();
- joyport_b = state_fio->FgetUint32();
+ joyport_a = state_fio->FgetUint32_BE();
+ joyport_b = state_fio->FgetUint32_BE();
intstat_opn = state_fio->FgetBool();
intstat_mouse = state_fio->FgetBool();
window_enabled = state_fio->FgetBool();
mmr_segment = state_fio->FgetUint8();
for(addr = 0; addr < 0x80; addr++) mmr_table[addr] = state_fio->FgetUint8();
- window_offset = state_fio->FgetUint32();
+ window_offset = state_fio->FgetUint32_BE();
#endif
- if(version == 1) stat = true;
+ }
+ if(version >= 2) {
+ event_beep = state_fio->FgetInt32_BE();
+ event_beep_oneshot = state_fio->FgetInt32_BE();
+ event_timerirq = state_fio->FgetInt32_BE();
}
// V2
- return stat;
+ return true;
}
// FD0E
void set_psg_cmd(uint8 cmd);
- void write_fd0f(void) {
- stat_romrammode = false;
- }
- uint8 read_fd0f(void) {
- stat_romrammode = true;
- return 0xff;
- }
- bool get_rommode_fd0f(void) {
- return stat_romrammode;
- }
+ void write_fd0f(void);
+ uint8 read_fd0f(void);
+ bool get_rommode_fd0f(void);
#if defined(_FM77AV_VARIANTS)
// FD12
uint8 subsystem_read_status(void);
Z80 *z80;
#endif
public:
- FM7_MAINIO(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
- {
- int i;
- p_vm = parent_vm;
- p_emu = parent_emu;
- kanjiclass1 = NULL;
- kanjiclass2 = NULL;
- opn_psg_77av = false;
- // FD00
- clock_fast = true;
- lpt_strobe = false;
- lpt_slctin = false;
- // FD01
- lpt_outdata = 0x00;
- // FD02
- cmt_indat = false; // bit7
- cmt_invert = false; // Invert signal
- lpt_det2 = false;
- lpt_det1 = false;
- lpt_pe = false;
- lpt_ackng_inv = false;
- lpt_error_inv = false;
- lpt_busy = false;
- // FD04
- stat_fdmode_2hd = false; // R/W : bit6, '0' = 2HD, '1' = 2DD. FM-77 Only.
- stat_kanjirom = true; // R/W : bit5, '0' = sub, '1' = main. FM-77 Only.
- stat_400linecard = false;// R/W : bit4, '0' = connected. FM-77 Only.
- stat_400linemode = false; // R/W : bit3, '0' = 400line, '1' = 200line.
- firq_break_key = false; // bit1, ON = '0'.
- firq_sub_attention = false; // bit0, ON = '0'.
- intmode_fdc = false; // bit2, '0' = normal, '1' = SFD.
- // FD05
- extdet_neg = false;
-#ifdef WITH_Z80
- z80_sel = false; // bit0 : '1' = Z80. Maybe only FM-7/77.
-#endif
- // FD06,07
- intstat_syndet = false;
- intstat_rxrdy = false;
- intstat_txrdy = false;
- // FD0B
- bootmode = 0x00;
- // FD0D
- // FD0F
- stat_romrammode = true; // ROM ON
-
- // FD15/ FD46 / FD51
- connect_opn = false;
- connect_whg = false;
- connect_thg = false;
-
- for(i = 0; i < 3; i++) {
- opn_address[i] = 0x00;
- opn_data[i] = 0x00;
- opn_cmdreg[i] = 0;
- }
- joyport_a = 0x00;
- joyport_b = 0x00;
-
- intstat_whg = false;
- intstat_thg = false;
- // FD17
- intstat_opn = false;
- intstat_mouse = false;
- mouse_enable = false;
- // FD18-FD1F
- connect_fdc = false;
- fdc_statreg = 0x00;
- fdc_cmdreg = 0x00;
- fdc_trackreg = 0x00;
- fdc_sectreg = 0x00;
- fdc_datareg = 0x00;
- fdc_headreg = 0x00;
- fdc_drvsel = 0x00;
- fdc_motor = false;
- irqstat_fdc = 0;
- // FD20, FD21, FD22, FD23
- connect_kanjiroml1 = false;
-#if defined(_FM77AV_VARIANTS)
- enable_initiator = true;
- // FD2C, FD2D, FD2E, FD2F
- connect_kanjiroml2 = false;
-#endif
-#if defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
- boot_ram = false;
-#endif
- memset(io_w_latch, 0x00, 0x100);
- }
- ~FM7_MAINIO(){}
+ FM7_MAINIO(VM* parent_vm, EMU* parent_emu);
+ ~FM7_MAINIO();
void event_vline(int v, int clock);
uint8 opn_regs[4][0x100];
- uint32 read_io8(uint32 addr) { // This is only for debug.
- addr = addr & 0xfff;
- if(addr < 0x100) {
- return io_w_latch[addr];
- } else if(addr < 0x500) {
- uint32 ofset = addr & 0xff;
- uint opnbank = (addr - 0x100) >> 8;
- return opn_regs[opnbank][ofset];
- } else if(addr < 0x600) {
-#if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX)
- return mmr_table[addr & 0xff];
-#elif defined(_FM77AV_VARIANTS) || defined(_FM77_VARIANTS)
- return mmr_table[addr & 0x3f];
-#else
- return 0xff;
-#endif
- }
- return 0xff;
- }
-
+ uint32 read_io8(uint32 addr); // This is only for debug.
+
void initialize();
void write_data8(uint32 addr, uint32 data);
void FM7_MAINMEM::reset()
{
+ int i;
waitfactor = 0;
waitcount = 0;
ioaccess_wait = false;
}
fm7_bootram[0x1fe] = 0xfe; // Set reset vector.
fm7_bootram[0x1ff] = 0x00; //
+ initiator_enabled = true;
+ boot_ram_write = true;
+#elif defined(_FM77_VARIANTS)
+ boot_ram_write = false;
#endif
+ bootmode = config.boot_mode & 3;
#if defined(HAS_MMR)
if((config.dipswitch & FM7_DIPSW_EXTRAM) != 0) {
extram_connected = true;
use_page2_extram = ((config.dipswitch & FM7_DIPSW_EXTRAM_AV) != 0) ? true : false;
}
#endif
+#ifdef HAS_MMR
+ for(i = 0x00; i < 0x80; i++) {
+ mmr_map_data[i] = 0;
+ }
+ mmr_segment = 0;
+ window_offset = 0;
+ mmr_enabled = false;
+ mmr_fast = false;
+ window_enabled = false;
+#endif
+ if(bootmode == 0) { // IF BASIC BOOT THEN ROM
+ basicrom_fd0f = true;
+ } else { // ELSE RAM
+ basicrom_fd0f = false;
+ }
//maincpu->reset();
+ clockmode = (config.cpu_type == 0) ? true : false;
+ is_basicrom = (bootmode == 0) ? true : false;
+ //if(bootmode < 4) bootmode = config.boot_mode & 3;
}
{
int waitfactor; // If MMR of TWR enabled, factor = 3.
// If memory, factor = 2?
- if(mainio->read_data8(FM7_MAINIO_CLOCKMODE) == FM7_MAINCLOCK_SLOW) return;
+ if(!clockmode) return; // SLOW
#ifdef HAS_MMR
if(!ioaccess_wait) {
waitfactor = 2;
ioaccess_wait = true;
} else { // Not MMR, TWR or enabled FAST MMR mode
waitfactor = 3; // If(MMR or TWR) and NOT FAST MMR factor = 3, else factor = 2
- if((mainio->read_data8(FM7_MAINIO_FASTMMR_ENABLED) != 0)) waitfactor = 2;
+ if(mmr_fast) waitfactor = 2;
ioaccess_wait = false;
}
- if((mainio->read_data8(FM7_MAINIO_WINDOW_ENABLED) == 0) &&
- (mainio->read_data8(FM7_MAINIO_MMR_ENABLED) == 0)) waitfactor = 2;
+ if((window_enabled) &&
+ (mmr_enabled)) waitfactor = 2;
#else
waitfactor = 2;
#endif
uint32 raddr = addr;
#ifdef HAS_MMR
if((addr < 0x8000) && (addr >= 0x7c00)) {
- raddr = ((mainio->read_data8(FM7_MAINIO_WINDOW_OFFSET) * 256) + addr) & 0x0ffff;
+ raddr = ((window_offset * 256) + addr) & 0x0ffff;
*realaddr = raddr;
#ifdef _FM77AV_VARIANTS
//printf("TWR hit %04x -> %04x\n", addr, raddr);
uint32 mmr_bank;
uint32 major_bank;
- //#ifdef _FM77AV_VARIANTS
#ifdef HAS_MMR
if(addr >= 0xfc00) return -1;
- //mmr_segment = mainio->read_data8(FM7_MAINIO_MMR_SEGMENT);
- mmr_bank = mainio->read_data8(FM7_MAINIO_MMR_BANK + ((addr >> 12) & 0x000f));
+ mmr_bank = mmr_map_data[(addr >> 12) & 0x000f | (mmr_segment << 4)] & 0x007f;
// Reallocated by MMR
// Bank 3x : Standard memories.
raddr = ((mmr_bank << 12) | raddr) & 0xffff;
return nonmmr_convert(raddr, realaddr);
}
-
#ifdef _FM77AV_VARIANTS
else if(mmr_bank == 0x3f) {
if((raddr >= 0xd80) && (raddr <= 0xd97)) { // MMR AREA
#elif defined(_FM77_VARIANTS)
else if(mmr_bank == 0x3f) {
if((raddr >= 0xc00) && (raddr < 0xe00)) {
- if(mainio->read_data8(FM7_MAINIO_IS_BASICROM) != 0) { // BASICROM enabled
+ if(is_basicrom) {
*realaddr = 0;
return FM7_MAINMEM_ZERO;
} else {
}
} else if(raddr >= 0xe00) {
*realaddr = addr - 0x0e00;
- if(mainio->read_data8(FM7_MAINIO_IS_BASICROM) != 0) { // BASICROM enabled
+ if(is_basicrom) {
if(diag_load_bootrom_mmr) {
return FM7_MAINMEM_BOOTROM_MMR;
} else {
}
}
#endif
- major_bank = (mmr_bank >> 4) & 0x0f;
-
+ major_bank = (mmr_bank >> 4) & 0x0f;
+
#ifdef _FM77AV_VARIANTS
-
if(major_bank == 0x0) { // PAGE 0
- *realaddr = ((mmr_bank << 12) | raddr) & 0x0ffff;
- return FM7_MAINMEM_AV_PAGE0;
- } else if(major_bank == 0x1) { // PAGE 1
- *realaddr = ((mmr_bank << 12) | raddr) & 0x0ffff;
- return FM7_MAINMEM_AV_DIRECTACCESS;
+ *realaddr = ((mmr_bank << 12) | raddr) & 0x0ffff;
+ return FM7_MAINMEM_AV_PAGE0;
+ } else if(major_bank == 0x1) { // PAGE 1
+ *realaddr = ((mmr_bank << 12) | raddr) & 0x0ffff;
+ return FM7_MAINMEM_AV_DIRECTACCESS;
} else if(major_bank == 0x2) { // PAGE 2
#if defined(CAPABLE_DICTROM)
- uint32 dbank = mainio->read_data8(FM7_MAINIO_EXTBANK);
- switch(mmr_bank) {
+ //uint32 dbank = mainio->read_data8(FM7_MAINIO_EXTBANK);
+ uint32 dbank = extbank;
+ switch(mmr_bank) {
case 0x28:
case 0x29: // Backuped RAM
if(((dbank & 0x80) != 0) && (dictrom_connected)){ // Battery backuped RAM
if(((dbank & 0x40) != 0) && (dictrom_connected)) { // Dictionary ROM
dbank = dbank & 0x3f;
uint32 extrom = mainio->read_data8(FM7_MAINIO_EXTROM) & 0x80;
+ //uint32 extrom = extrom_bank;
if(extrom == 0) { // Dictionary selected.
dbank = dbank << 12;
*realaddr = raddr | dbank;
}
}
break;
- }
- *realaddr = (raddr | (mmr_bank << 12)) & 0x0ffff;
- return FM7_MAINMEM_AV_PAGE2;
-#else
- //*realaddr = (raddr | (mmr_bank << 12)) & 0x0ffff;
- if(use_page2_extram) {
- *realaddr = ((mmr_bank << 12) | raddr) & 0x0ffff;
+ }
+ *realaddr = (raddr | (mmr_bank << 12)) & 0x0ffff;
return FM7_MAINMEM_AV_PAGE2;
- }
- *realaddr = 0;
- return FM7_MAINMEM_NULL;
-
+#else
+ //*realaddr = (raddr | (mmr_bank << 12)) & 0x0ffff;
+ if(use_page2_extram) {
+ *realaddr = ((mmr_bank << 12) | raddr) & 0x0ffff;
+ return FM7_MAINMEM_AV_PAGE2;
+ }
#endif
- // RAM
}
-# if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX) || defined(_FM77AV20)
+#endif
+#if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX)
else if(extram_connected) { // PAGE 4-
- if((mmr_bank >> 4) >= (extram_pages + 4)) {
+ if(major_bank >= (extram_pages + 4)) {
*realaddr = 0;
return FM7_MAINMEM_NULL; // $FF
} else {
return FM7_MAINMEM_NULL;
}
}
-#endif
-#else // 77
- // page 0 or 1 or 2.
- if(extram_connected) {
- if(major_bank >= extram_pages) {
+#elif defined(_FM77_VARIANTS)
+ if(extram_connected) { // PAGE 4-
+ if((major_bank > extram_pages) || (major_bank >= 3)) {
*realaddr = 0;
- return FM7_MAINMEM_NULL;
- } else { // EXTRAM Exists.
- raddr = ((mmr_bank << 12) | raddr) & 0x3ffff;
+ return FM7_MAINMEM_NULL; // $FF
+ } else {
+ raddr = ((uint32)mmr_bank << 12) | raddr;
*realaddr = raddr;
return FM7_MAINMEM_EXTRAM;
}
+ } else {
+ *realaddr = 0;
+ return FM7_MAINMEM_NULL; // $FF
+ }
+#else // _FM77AV_VARIANTS
+ if(major_bank > 3) {
+ *realaddr = 0;
+ return FM7_MAINMEM_NULL; // $FF
}
#endif
-#endif
+#endif // HAS_MMR
+ *realaddr = 0;
return -1;
}
{
addr &= 0x0ffff;
#ifdef _FM77AV_VARIANTS
- if(mainio->read_data8(FM7_MAINIO_INITROM_ENABLED) != 0) {
+ if(initiator_enabled) {
if((addr >= 0x6000) && (addr < 0x8000)) {
+ //printf("HIT %02x\n", read_table[FM7_MAINMEM_INITROM].memory[addr - 0x6000]);
*realaddr = addr - 0x6000;
return FM7_MAINMEM_INITROM;
}
return FM7_MAINMEM_OMOTE;
} else if(addr < 0xfc00) {
*realaddr = addr - 0x8000;
- if(mainio->read_data8(FM7_MAINIO_READ_FD0F) != 0) {
+ if(basicrom_fd0f) {
return FM7_MAINMEM_BASICROM;
}
return FM7_MAINMEM_URA;
#if defined(_FM77AV_VARIANTS)
return FM7_MAINMEM_BOOTROM_RAM;
#else
- switch(mainio->read_data8(FM7_MAINIO_BOOTMODE)) {
+ switch(bootmode) {
case 0:
return FM7_MAINMEM_BOOTROM_BAS;
break;
int FM7_MAINMEM::getbank(uint32 addr, uint32 *realaddr)
{
if(realaddr == NULL) return FM7_MAINMEM_NULL; // Not effect.
- addr = addr & 0xffff;
#ifdef HAS_MMR
- if(mainio->read_data8(FM7_MAINIO_WINDOW_ENABLED) != 0) {
+ if(window_enabled) {
int stat;
uint32 raddr;
stat = window_convert(addr, &raddr);
return stat;
}
}
- if(mainio->read_data8(FM7_MAINIO_MMR_ENABLED) != 0) {
+ if(mmr_enabled) {
int stat;
uint32 raddr;
stat = mmr_convert(addr, &raddr);
}
}
#endif
+ addr = addr & 0xffff;
// NOT MMR.
return nonmmr_convert(addr, realaddr);
}
case SIG_FM7_SUB_HALT:
sub_halted = flag;
break;
+ case FM7_MAINIO_IS_BASICROM:
+ is_basicrom = flag;
+ break;
+ case FM7_MAINIO_PUSH_FD0F:
+ basicrom_fd0f = flag;
+ break;
+ case FM7_MAINIO_CLOCKMODE:
+ clockmode = flag;
+ break;
+ case FM7_MAINIO_BOOTMODE:
+ bootmode = data & 0x07;
+ break;
+#if defined(_FM77AV_VARIANTS) || defined(_FM77_VARIANTS)
+ case FM7_MAINIO_BOOTRAM_RW:
+ bootmode = flag;
+ break;
+#endif
+#ifdef _FM77AV_VARIANTS
+ case FM7_MAINIO_INITROM_ENABLED:
+ initiator_enabled = flag;
+ break;
+ case FM7_MAINIO_EXTBANK:
+ extcard_bank = data & 0xff;
+ break;
+ case FM7_MAINIO_EXTROM:
+ extrom_bank = data & 0xff;
+ break;
+#endif
+#ifdef HAS_MMR
+ case FM7_MAINIO_WINDOW_ENABLED:
+ window_enabled = flag;
+ break;
+ case FM7_MAINIO_FASTMMR_ENABLED:
+ mmr_fast = flag;
+ break;
+ case FM7_MAINIO_MMR_ENABLED:
+ mmr_enabled = flag;
+ break;
+#endif
}
}
emu->out_debug_log("Illegal BANK: ADDR = %04x", addr);
return 0xff; // Illegal
}
-
- if(bank == FM7_MAINMEM_SHAREDRAM) {
- //sub_halted = (display->read_signal(SIG_DISPLAY_HALT) == 0) ? false : true;
- if(!sub_halted) return 0xff; // Not halt
- return display->read_data8(realaddr + 0xd380); // Okay?
- } else if(bank == FM7_MAINMEM_MMIO) {
- return mainio->read_data8(realaddr);
+ if(bank == FM7_MAINMEM_SHAREDRAM) {
+ if(!sub_halted) return 0xff; // Not halt
+ return display->read_data8(realaddr + 0xd380); // Okay?
+ //} else if(bank == FM7_MAINMEM_MMIO) {
+ // return mainio->read_data8(realaddr);
} else if(bank == FM7_MAINMEM_NULL) {
return 0xff;
}
#if defined(_FM77AV_VARIANTS)
else if(bank == FM7_MAINMEM_AV_DIRECTACCESS) {
- //sub_halted = (display->read_signal(SIG_DISPLAY_HALT) == 0) ? false : true;
if(!sub_halted) return 0xff; // Not halt
return display->read_data8(realaddr); // Okay?
}
#endif
- else if(read_table[bank].memory != NULL) {
+ else if(read_table[bank].dev != NULL) {
+ return read_table[bank].dev->read_data8(realaddr);
+ } else if(read_table[bank].memory != NULL) {
return read_table[bank].memory[realaddr];
}
return 0xff; // Dummy
{
uint32 realaddr;
int bank;
-
+ if(addr >= FM7_MAINIO_WINDOW_OFFSET) {
+ switch(addr) {
+ case FM7_MAINIO_WINDOW_OFFSET:
+ window_offset = data;
+ break;
+ case FM7_MAINIO_MMR_SEGMENT:
+ mmr_segment = data & 0x0f;
+ break;
+ default:
+ if((addr >= FM7_MAINIO_MMR_BANK) && (addr < (FM7_MAINIO_MMR_BANK + 0x80))){
+ mmr_map_data[addr - FM7_MAINIO_MMR_BANK] = (uint8)data;
+ }
+ break;
+ }
+ return;
+ }
bank = getbank(addr, &realaddr);
if(bank < 0) {
emu->out_debug_log("Illegal BANK: ADDR = %04x", addr);
return; // Illegal
}
-
- if(bank == FM7_MAINMEM_SHAREDRAM) {
- //sub_halted = (display->read_signal(SIG_DISPLAY_HALT) == 0) ? false : true;
- if(!sub_halted) return; // Not halt
+ if(bank == FM7_MAINMEM_SHAREDRAM) {
+ if(!sub_halted) return; // Not halt
display->write_data8(realaddr + 0xd380, data); // Okay?
return;
- } else if(bank == FM7_MAINMEM_MMIO) {
- mainio->write_data8(realaddr, (uint8)data);
- return;
+ //} else if(bank == FM7_MAINMEM_MMIO) {
+ // mainio->write_data8(realaddr, (uint8)data);
+ // return;
} else if(bank == FM7_MAINMEM_NULL) {
return;
}
#if defined(_FM77AV_VARIANTS)
else if(bank == FM7_MAINMEM_AV_DIRECTACCESS) {
- //sub_halted = (display->read_signal(SIG_DISPLAY_HALT) == 0) ? false : true;
if(!sub_halted) return; // Not halt
- display->write_data8(realaddr, data); // Okay?
- return;
+ display->write_data8(realaddr, data); // Okay?
+ return;
}
#endif
#if defined(HAS_MMR)
else if(bank == FM7_MAINMEM_BOOTROM_RAM) {
- if(mainio->read_data8(FM7_MAINIO_BOOTMODE) != 4) return;
+ if(!boot_ram_write) return;
write_table[bank].memory[realaddr] = (uint8)data;
+ return;
}
#endif
- else if(write_table[bank].memory != NULL) {
+ else if(write_table[bank].dev != NULL) {
+ write_table[bank].dev->write_data8(realaddr, data);
+ } else if(write_table[bank].memory != NULL) {
write_table[bank].memory[realaddr] = (uint8)data;
}
}
#if defined(_FM77AV_VARIANTS)
dictrom_connected = false;
#endif
+#ifdef HAS_MMR
+ for(i = 0x00; i < 0x80; i++) {
+ mmr_map_data[i] = 0;
+ }
+ mmr_segment = 0;
+ window_offset = 0;
+ mmr_enabled = false;
+ mmr_fast = false;
+ window_enabled = false;
+#endif
+#ifdef _FM77AV_VARIANTS
+ extcard_bank = 0;
+ extrom_bank = 0;
+ initiator_enabled = true;
+ boot_ram_write = true;
+#endif
+ bootmode = config.boot_mode & 3;
+ basicrom_fd0f = false;
+ is_basicrom = (bootmode == 0) ? true : false;
// Initialize table
// $0000-$7FFF
memset(read_table, 0x00, sizeof(read_table));
// MEMORY::release();
}
-#define STATE_VERSION 1
+#define STATE_VERSION 2
void FM7_MAINMEM::save_state(FILEIO *state_fio)
{
int pages;
int addr;
- state_fio->FputUint32(STATE_VERSION);
- state_fio->FputInt32(this_device_id);
+ state_fio->FputUint32_BE(STATE_VERSION);
+ state_fio->FputInt32_BE(this_device_id);
// V1
state_fio->FputBool(ioaccess_wait);
- state_fio->FputInt32(waitfactor);
- state_fio->FputInt32(waitcount);
+ state_fio->FputInt32_BE(waitfactor);
+ state_fio->FputInt32_BE(waitcount);
state_fio->FputBool(sub_halted);
#ifdef HAS_MMR
state_fio->FputBool(extram_connected);
# if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX) || defined(_FM77AV20) || defined(_FM77_VARIANTS)
- state_fio->FputInt32(extram_pages);
+ state_fio->FputInt32_BE(extram_pages);
pages = extram_pages;
# if defined(_FM77_VARIANTS)
if(pages > 3) pages = 3;
# endif
# endif
#endif
+
+ { // V2;
+ state_fio->FputBool(is_basicrom);
+ state_fio->FputBool(clockmode);
+ state_fio->FputBool(basicrom_fd0f);
+ state_fio->FputUint32_BE(bootmode);
+#if defined(_FM77AV_VARIANTS)
+ state_fio->FputUint32_BE(extcard_bank);
+ state_fio->FputUint32_BE(extrom_bank);
+ state_fio->FputBool(initiator_enabled);
+#endif
+#if defined(_FM77AV_VARIANTS) || defined(_FM77_VARIANTS)
+ state_fio->FputBool(boot_ram_write);
+#endif
+#if defined(HAS_MMR)
+ state_fio->FputBool(window_enabled);
+ state_fio->FputBool(mmr_enabled);
+ state_fio->FputBool(mmr_fast);
+ state_fio->FputUint16_BE(window_offset);
+ state_fio->FputUint8(mmr_segment);
+ state_fio->Fwrite(mmr_map_data, sizeof(mmr_map_data), 1);
+#endif
+ }
}
bool FM7_MAINMEM::load_state(FILEIO *state_fio)
int addr;
bool stat = false;
uint32 version;
- version = state_fio->FgetUint32();
- if(this_device_id != state_fio->FgetInt32()) return false;
+ version = state_fio->FgetUint32_BE();
+ if(this_device_id != state_fio->FgetInt32_BE()) return false;
if(version >= 1) {
// V1
ioaccess_wait = state_fio->FgetBool();
- waitfactor = state_fio->FgetInt32();
- waitcount = state_fio->FgetInt32();
+ waitfactor = state_fio->FgetInt32_BE();
+ waitcount = state_fio->FgetInt32_BE();
sub_halted = state_fio->FgetBool();
#ifdef HAS_MMR
extram_connected = state_fio->FgetBool();
# if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX) || defined(_FM77AV20) || defined(_FM77_VARIANTS)
- extram_pages = state_fio->FgetInt32();
+ extram_pages = state_fio->FgetInt32_BE();
pages = extram_pages;
# if defined(_FM77_VARIANTS)
if(pages > 3) pages = 3;
#endif
if(version == 1) return true;
}
- return false;
+ if(version >= 2) { // V2;
+ is_basicrom = state_fio->FgetBool();
+ clockmode = state_fio->FgetBool();
+ basicrom_fd0f = state_fio->FgetBool();
+ bootmode = state_fio->FgetUint32_BE();
+#if defined(_FM77AV_VARIANTS)
+ extcard_bank = state_fio->FgetUint32_BE();
+ extrom_bank = state_fio->FgetUint32_BE();
+ initiator_enabled = state_fio->FgetBool();
+#endif
+#if defined(_FM77AV_VARIANTS) || defined(_FM77_VARIANTS)
+ boot_ram_write = state_fio->FgetBool();
+#endif
+#if defined(HAS_MMR)
+ window_enabled = state_fio->FgetBool();
+ mmr_enabled = state_fio->FgetBool();
+ mmr_fast = state_fio->FgetBool();
+ window_offset = state_fio->FgetUint16_BE();
+ mmr_segment = state_fio->FgetUint8();
+ state_fio->Fread(mmr_map_data, sizeof(mmr_map_data), 1);
+#endif
+ }
+ return true;
}
int waitfactor;
int waitcount;
bool sub_halted;
+ // V2
+#ifdef HAS_MMR
+ bool window_enabled;
+ bool mmr_enabled;
+ bool mmr_fast;
+ uint16 window_offset;
+ uint8 mmr_segment;
+ uint8 mmr_map_data[0x80];
+#endif
+ bool is_basicrom;
+ bool clockmode;
+ bool basicrom_fd0f;
+ uint32 bootmode;
+#ifdef _FM77AV_VARIANTS
+ uint32 extcard_bank;
+ uint32 extrom_bank;
+ bool initiator_enabled;
+#endif
+#if defined(_FM77AV_VARIANTS) || defined(_FM77_VARIANTS)
+ bool boot_ram_write;
+#endif
protected:
EMU *p_emu;
VM *p_vm;
double usec;
bool lastflag = false;
- //is_400line = (target->read_signal(SIG_DISPLAY_MODE_IS_400LINE) != 0) ? true : false;
- planes = target->read_signal(SIG_DISPLAY_PLANES) & 0x07;
- screen_width = target->read_signal(SIG_DISPLAY_X_WIDTH) * 8;
- screen_height = target->read_signal(SIG_DISPLAY_Y_HEIGHT);
//if((command_reg & 0x80) == 0) return;
oldaddr = 0xffffffff;
if((id >= ALU_WRITE_PROXY) && (id < (ALU_WRITE_PROXY + 0x18000))) {
uint32 dmydata;
raddr = id - ALU_WRITE_PROXY;
- //is_400line = (target->read_signal(SIG_DISPLAY_MODE_IS_400LINE) != 0) ? true : false;
if(is_400line) {
raddr = raddr & 0x7fff;
} else {
case SIG_ALU_MULTIPAGE:
multi_page = (data & mask) & 0x07;
break;
+ case SIG_ALU_PLANES:
+ planes = (data & mask) & 0x07;
+ if(planes >= 4) planes = 4;
+ break;
+ case SIG_ALU_X_WIDTH:
+ screen_width = (data << 3) & 0x3ff;
+ break;
+ case SIG_ALU_Y_HEIGHT:
+ screen_height = data & 0x3ff;
+ break;
}
}
is_400line = false;
eventid_busy = -1;
multi_page = 0x00;
+ planes = 3;
+ screen_width = 640;
+ screen_height = 200;
}
void MB61VH010::reset(void)
line_ybegin.d = 0; // D426-D427 (WO)
line_xend.d = 0; // D428-D429 (WO)
line_yend.d = 0; // D42A-D42B (WO)
-
oldaddr = 0xffffffff;
- planes = target->read_signal(SIG_DISPLAY_PLANES) & 0x07;
if(planes >= 4) planes = 4;
- //is_400line = (target->read_signal(SIG_DISPLAY_MODE_IS_400LINE) != 0) ? true : false;
-
- screen_width = target->read_signal(SIG_DISPLAY_X_WIDTH) * 8;
- screen_height = target->read_signal(SIG_DISPLAY_Y_HEIGHT);
+}
+
+#define STATE_VERSION 1
+void MB61VH010::save_state(FILEIO *state_fio)
+{
+ int i;
+ state_fio->FputUint32(STATE_VERSION);
+ state_fio->FputInt32(this_device_id);
+
+ { // V1
+ state_fio->FputUint8(command_reg);
+ state_fio->FputUint8(color_reg);
+ state_fio->FputUint8(mask_reg);
+ state_fio->FputUint8(cmp_status_reg);
+ for(i = 0; i < 8; i++) state_fio->FputUint8(cmp_color_data[i]);
+ state_fio->FputUint8(bank_disable_reg);
+ for(i = 0; i < 4; i++) state_fio->FputUint8(tile_reg[i]);
+ state_fio->FputUint8(multi_page);
+
+ state_fio->FputUint32_BE(line_addr_offset.d);
+ state_fio->FputUint16_BE(line_pattern.w.l);
+ state_fio->FputUint16_BE(line_xbegin.w.l);
+ state_fio->FputUint16_BE(line_ybegin.w.l);
+ state_fio->FputUint16_BE(line_xend.w.l);
+ state_fio->FputUint16_BE(line_yend.w.l);
+
+ state_fio->FputBool(busy_flag);
+ state_fio->FputInt32_BE(eventid_busy);
+
+ state_fio->FputUint32_BE(total_bytes);
+ state_fio->FputUint32_BE(oldaddr);
+ state_fio->FputUint32_BE(alu_addr);
+
+ state_fio->FputUint32_BE(planes);
+ state_fio->FputBool(is_400line);
+ state_fio->FputUint32_BE(screen_width);
+ state_fio->FputUint32_BE(screen_height);
+
+ state_fio->FputUint16_BE(line_style.w.l);
+ }
+
+}
+
+bool MB61VH010::load_state(FILEIO *state_fio)
+{
+ uint32 version = state_fio->FgetUint32();
+ int i;
+
+ if(this_device_id != state_fio->FgetInt32()) return false;
+ if(version >= 1) {
+ command_reg = state_fio->FgetUint8();
+ color_reg = state_fio->FgetUint8();
+ mask_reg = state_fio->FgetUint8();
+ cmp_status_reg = state_fio->FgetUint8();
+ for(i = 0; i < 8; i++) cmp_color_data[i] = state_fio->FgetUint8();
+ bank_disable_reg = state_fio->FgetUint8();
+ for(i = 0; i < 4; i++) tile_reg[i] = state_fio->FgetUint8();
+ multi_page = state_fio->FgetUint8();
+
+ line_addr_offset.d = state_fio->FgetUint32_BE();
+ line_pattern.d = 0;
+ line_xbegin.d = 0;
+ line_ybegin.d = 0;
+ line_xend.d = 0;
+ line_yend.d = 0;
+
+ line_pattern.w.l = state_fio->FgetUint16_BE();
+ line_xbegin.w.l = state_fio->FgetUint16_BE();
+ line_ybegin.w.l = state_fio->FgetUint16_BE();
+ line_xend.w.l = state_fio->FgetUint16_BE();
+ line_yend.w.l = state_fio->FgetUint16_BE();
+
+ busy_flag = state_fio->FgetBool();
+ eventid_busy = state_fio->FgetInt32_BE();
+
+ total_bytes = state_fio->FgetUint32_BE();
+ oldaddr = state_fio->FgetUint32_BE();
+ alu_addr = state_fio->FgetUint32_BE();
+
+ planes = state_fio->FgetUint32_BE();
+ is_400line = state_fio->FgetBool();
+ screen_width = state_fio->FgetUint32_BE();
+ screen_height = state_fio->FgetUint32_BE();
+
+ line_style.d = 0;
+ line_style.w.l = state_fio->FgetUint16_BE();
+ }
}
SIG_ALU_BUSYSTAT = 1,
SIG_ALU_400LINE,
SIG_ALU_MULTIPAGE,
+ SIG_ALU_PLANES,
+ SIG_ALU_X_WIDTH,
+ SIG_ALU_Y_HEIGHT,
};
enum {
MB61VH010(VM *parent_vm, EMU *parent_emu);
~MB61VH010();
+ void save_state(FILEIO *state_fio);
+ bool load_state(FILEIO *state_fio);
void event_callback(int event_id, int err);
void write_data8(uint32 id, uint32 data);
uint32 read_data8(uint32 addr);
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