drm: rcar-du: Fix display timing controller parameter

There is a bug in the setting of the DES (Display Enable Signal)
register. This current setting occurs 1 dot left shift. The DES
register should be set minus one value about the specifying value
with H/W specification. This patch corrects it.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 7316fc7..aca26ee 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -172,7 +172,7 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
                                        mode->crtc_vsync_start - 1);
        rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 
-       rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start);
+       rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start - 1);
        rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 }