signal dma_cnt_ce_n : std_logic_vector(0 downto 0);
signal dma_cnt_ce : std_logic;
signal dma_start_n : std_logic;
+signal dma_write_we_n : std_logic;
signal dma_end_n : std_logic;
signal dma_process_n : std_logic;
signal dma_rst_n : std_logic;
-signal dma_status_we_n : std_logic;
signal dma_status : std_logic_vector(1 downto 0);
signal dma_next_status : std_logic_vector(1 downto 0);
constant DMA_ST_IDLE : std_logic_vector(1 downto 0) := "00";
constant DMA_ST_SETUP : std_logic_vector(1 downto 0) := "01";
constant DMA_ST_PROCESS : std_logic_vector(1 downto 0) := "10";
+constant DMA_ST_COMPLETE : std_logic_vector(1 downto 0) := "11";
begin
port map (clk, dma_rst_n, dma_cnt_ce, '1', (others => '0'),
dma_addr(dsize - 1 downto 0));
dma_h_inst : d_flip_flop generic map(dsize)
- port map (clk_n, '1', '1', dma_start_n, cpu_d,
+ port map (clk_n, '1', '1', dma_write_we_n, cpu_d,
dma_addr(dsize * 2 - 1 downto dsize));
dma_status_inst : d_flip_flop generic map(2)
- port map (clk_n, rst_n, '1', dma_status_we_n, dma_next_status, dma_status);
+ port map (clk_n, rst_n, '1', '0', dma_next_status, dma_status);
dma_val_inst : d_flip_flop generic map(dsize)
port map (clk_n, rst_n, '1', dma_process_n, cpu_d, oam_data);
- --apu register access process
- reg_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d)
+ dma_write_we_n <= '0'
+ when (ce_n = '0' and r_nw = '0'and cpu_addr(4 downto 0) = OAM_DMA) else
+ '1';
+
+ --dma start process
+ reg_set_p : process (rst_n, clk_n)
begin
if (rst_n = '0') then
- --cpu_d <= (others => 'Z');
dma_start_n <= '1';
- elsif (rising_edge(clk)) then
- if (ce_n = '0') then
- if (r_nw = '0') then
- --apu write
- --cpu_d <= (others => 'Z');
- if (cpu_addr(4 downto 0) = OAM_DMA) then
- dma_start_n <= '0';
- else
- dma_start_n <= '1';
- end if;
- elsif (r_nw = '1') then
- dma_start_n <= '1';
-
- --joy pad read
- if (cpu_addr(4 downto 0) = OAM_JP1) then
- --cpu_d <= (others => '0');
- elsif (cpu_addr(4 downto 0) = OAM_JP2) then
- --cpu_d <= (others => '0');
- else
- --return dummy zero vale.
- --cpu_d <= (others => '0');
- end if;
- end if;
+ rdy <= '1';
+ elsif (rising_edge(clk_n)) then
+ if (ce_n = '0' and r_nw = '0' and cpu_addr(4 downto 0) = OAM_DMA) then
+ dma_start_n <= '0';
else
- --cpu_d <= (others => 'Z');
dma_start_n <= '1';
end if; --if (ce_n = '0')
+
+ if (ce_n = '0' and r_nw = '0' and cpu_addr(4 downto 0) = OAM_DMA) then
+ --pull rdy pin down to stop cpu bus accessing.
+ rdy <= '0';
+ elsif (dma_end_n = '0') then
+ --pull rdy pin up to re-enable cpu bus accessing.
+ rdy <= '1';
+ end if; --if (ce_n = '0')
end if; --if (rst_n = '0') then
end process;
begin
if (rst_n = '0') then
dma_next_status <= DMA_ST_IDLE;
- dma_status_we_n <= '1';
dma_end_n <= '1';
dma_process_n <= '1';
cpu_addr <= (others => 'Z');
elsif (rising_edge(clk)) then
if (dma_status = DMA_ST_IDLE) then
if (dma_start_n = '0') then
- dma_status_we_n <= '0';
dma_next_status <= DMA_ST_SETUP;
+ else
+ dma_next_status <= DMA_ST_IDLE;
end if;
- dma_process_n <= '1';
dma_end_n <= '1';
+ dma_process_n <= '1';
cpu_addr <= (others => 'Z');
cpu_d <= (others => 'Z');
r_nw <= 'Z';
elsif (dma_status = DMA_ST_SETUP) then
cpu_addr <= OAMADDR;
- cpu_d <= (others => '0');
+ cpu_d <= dma_addr(dsize * 2 - 1 downto dsize);
r_nw <= '0';
dma_next_status <= DMA_ST_PROCESS;
elsif (dma_status = DMA_ST_PROCESS) then
if (dma_addr(dsize - 1 downto 0) = "11111111" and dma_cnt_ce_n(0) = '1') then
- dma_status_we_n <= '0';
- dma_next_status <= DMA_ST_IDLE;
- dma_end_n <= '0';
+ dma_next_status <= DMA_ST_COMPLETE;
else
- dma_status_we_n <= '1';
+ dma_next_status <= DMA_ST_PROCESS;
dma_process_n <= '0';
- dma_end_n <= '1';
end if;
if (dma_cnt_ce_n(0) = '0') then
cpu_addr <= OAMDATA;
cpu_d <= oam_data;
end if;
+ elsif (dma_status = DMA_ST_COMPLETE) then
+ dma_next_status <= DMA_ST_IDLE;
+ dma_process_n <= '1';
+ dma_end_n <= '0';
+ r_nw <= 'Z';
+ cpu_addr <= (others => 'Z');
+ cpu_d <= (others => 'Z');
end if;--if (dma_status = DMA_ST_IDLE) then
end if;--if (rst_n = '0') then
end process;
- rdy_p : process (rst_n, clk_n)
- begin
- if (rst_n = '0') then
- rdy <= '1';
- elsif (rising_edge(clk_n)) then
- if (dma_start_n = '0') then
- --pull rdy pin down to stop cpu bus accessing.
- rdy <= '0';
- elsif (dma_end_n = '0') then
- --pull rdy pin up to re-enable cpu bus accessing.
- rdy <= '1';
- else
- rdy <= '1';
- end if;
- end if;
- end process;
+-- --joy pad process..
+-- jp_p : process (rst_n, clk_n)
+-- begin
+-- if (rst_n = '0') then
+-- cpu_d <= (others => 'Z');
+-- elsif (rising_edge(clk)) then
+-- if (ce_n = '0' and r_nw = '1') then
+-- --joy pad read
+-- --return dummy zero vale.
+-- if (cpu_addr(4 downto 0) = OAM_JP1) then
+-- cpu_d <= (others => '0');
+-- elsif (cpu_addr(4 downto 0) = OAM_JP2) then
+-- cpu_d <= (others => '0');
+-- else
+-- cpu_d <= (others => 'Z');
+-- end if;
+-- else
+-- cpu_d <= (others => 'Z');
+-- end if; --if (ce_n = '0')
+-- end if; --if (rst_n = '0') then
+-- end process;
end rtl;
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+entity mos6502 is \r
+ generic ( dsize : integer := 8;\r
+ asize : integer :=16\r
+ );\r
+ port ( \r
+ signal dbg_instruction : out std_logic_vector(7 downto 0);\r
+ signal dbg_int_d_bus : out std_logic_vector(7 downto 0);\r
+ signal dbg_exec_cycle : out std_logic_vector (5 downto 0);\r
+ signal dbg_ea_carry : out std_logic;\r
+\r
+-- signal dbg_index_bus : out std_logic_vector(7 downto 0);\r
+-- signal dbg_acc_bus : out std_logic_vector(7 downto 0);\r
+ signal dbg_status : out std_logic_vector(7 downto 0);\r
+ signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);\r
+ signal dbg_dec_oe_n : out std_logic;\r
+ signal dbg_dec_val : out std_logic_vector (7 downto 0);\r
+ signal dbg_int_dbus : out std_logic_vector (7 downto 0);\r
+-- signal dbg_status_val : out std_logic_vector (7 downto 0);\r
+ signal dbg_stat_we_n : out std_logic;\r
+ signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w : out std_logic_vector (7 downto 0);\r
+\r
+ input_clk : in std_logic; --phi0 input pin.\r
+ rdy : in std_logic;\r
+ rst_n : in std_logic;\r
+ irq_n : in std_logic;\r
+ nmi_n : in std_logic;\r
+ dbe : in std_logic;\r
+ r_nw : out std_logic;\r
+ phi1 : out std_logic;\r
+ phi2 : out std_logic;\r
+ addr : out std_logic_vector ( asize - 1 downto 0);\r
+ d_io : inout std_logic_vector ( dsize - 1 downto 0)\r
+ );\r
+end mos6502;\r
+\r
+architecture rtl of mos6502 is\r
+\r
+\r
+begin\r
+ phi1 <= input_clk;\r
+ phi2 <= not input_clk;\r
+\r
+ --set ppu value...\r
+ set_ppu_p : process (input_clk, rst_n)\r
+ use ieee.std_logic_arith.conv_std_logic_vector;\r
+\r
+ variable init_step_cnt, plt_step_cnt, \r
+ nt_step_cnt, spr_step_cnt, dma_step_cnt, enable_ppu_step_cnt : integer;\r
+ variable init_done : std_logic;\r
+ variable global_step_cnt : integer;\r
+ constant cpu_io_multi : integer := 3; --io happens every 4 cpu cycle.\r
+ variable i, j : integer;\r
+ variable ch : integer := 16#41# ;\r
+\r
+procedure io_out (ad: in integer; dt : in integer) is\r
+begin\r
+ r_nw <= '0';\r
+ addr <= conv_std_logic_vector(ad, 16);\r
+ d_io <= conv_std_logic_vector(dt, 8);\r
+end;\r
+procedure io_brk is\r
+begin\r
+ addr <= (others => 'Z');\r
+ d_io <= (others => 'Z');\r
+ r_nw <= 'Z';\r
+end;\r
+\r
+ begin\r
+ if (rst_n = '0') then\r
+ \r
+ r_nw <= 'Z';\r
+ addr <= (others => 'Z');\r
+ d_io <= (others => 'Z');\r
+ \r
+ init_done := '0';\r
+ global_step_cnt := 0;\r
+ init_step_cnt := 0;\r
+ plt_step_cnt := 0;\r
+ nt_step_cnt := 0;\r
+ spr_step_cnt := 0;\r
+ dma_step_cnt := 0;\r
+ enable_ppu_step_cnt := 0;\r
+\r
+ elsif (rising_edge(input_clk)) then\r
+\r
+ if (rdy = '1') then\r
+ if (init_done = '0') then\r
+ if (global_step_cnt = 0) then\r
+ --step0.0 = init ppu.\r
+ if (init_step_cnt = 0 * cpu_io_multi) then\r
+ --PPUCTRL=00\r
+ io_out(16#2000#, 16#00#);\r
+ elsif (init_step_cnt = 1 * cpu_io_multi) then\r
+ --PPUMASK=00\r
+ io_out(16#2001#, 16#00#);\r
+ else\r
+ io_brk;\r
+ if (init_step_cnt > 2 * cpu_io_multi) then\r
+ global_step_cnt := global_step_cnt + 1;\r
+ end if;\r
+ end if;\r
+ init_step_cnt := init_step_cnt + 1;\r
+ elsif (global_step_cnt = 1) then\r
+ --step0.1 = palette set.\r
+ --palettes:\r
+ --;;;bg palette\r
+ -- .byte $0f, $00, $10, $20\r
+ -- .byte $0f, $04, $14, $24\r
+ -- .byte $0f, $08, $18, $28\r
+ -- .byte $0f, $0c, $1c, $2c\r
+ --;;;spr palette\r
+ -- .byte $0f, $00, $10, $20\r
+ -- .byte $0f, $06, $16, $26\r
+ -- .byte $0f, $08, $18, $28\r
+ -- .byte $0f, $0a, $1a, $2a\r
+ \r
+ \r
+ if (plt_step_cnt = 0 * cpu_io_multi) then\r
+ --set vram addr 3f00\r
+ io_out(16#2006#, 16#3f#);\r
+ elsif (plt_step_cnt = 1 * cpu_io_multi) then\r
+ io_out(16#2006#, 16#00#);\r
+ \r
+ elsif (plt_step_cnt = 2 * cpu_io_multi) then\r
+ --set palette bg data\r
+ io_out(16#2007#, 16#11#);\r
+ elsif (plt_step_cnt = 3 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#01#);\r
+ elsif (plt_step_cnt = 4 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#03#);\r
+ elsif (plt_step_cnt = 5 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#13#);\r
+\r
+ elsif (plt_step_cnt = 6 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#0f#);\r
+ elsif (plt_step_cnt = 7 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#04#);\r
+ elsif (plt_step_cnt = 8 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#14#);\r
+ elsif (plt_step_cnt = 9 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#24#);\r
+ \r
+ elsif (plt_step_cnt = 10 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#0f#);\r
+ elsif (plt_step_cnt = 11 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#08#);\r
+ elsif (plt_step_cnt = 12 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#18#);\r
+ elsif (plt_step_cnt = 13 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#28#);\r
+ \r
+ elsif (plt_step_cnt = 14 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#05#);\r
+ elsif (plt_step_cnt = 15 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#0c#);\r
+ elsif (plt_step_cnt = 16 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#1c#);\r
+ elsif (plt_step_cnt = 17 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#2c#);\r
+\r
+ elsif (plt_step_cnt = 18 * cpu_io_multi) then\r
+ --below is sprite pallete\r
+ io_out(16#2007#, 16#00#);\r
+ elsif (plt_step_cnt = 19 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#24#);\r
+ elsif (plt_step_cnt = 20 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#1b#);\r
+ elsif (plt_step_cnt = 21 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#11#);\r
+\r
+ elsif (plt_step_cnt = 22 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#00#);\r
+ elsif (plt_step_cnt = 23 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#32#);\r
+ elsif (plt_step_cnt = 24 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#16#);\r
+ elsif (plt_step_cnt = 25 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#20#);\r
+\r
+ elsif (plt_step_cnt = 26 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#00#);\r
+ elsif (plt_step_cnt = 27 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#26#);\r
+ elsif (plt_step_cnt = 28 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#01#);\r
+ elsif (plt_step_cnt = 29 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#31#);\r
+\r
+ else\r
+ io_brk;\r
+ if (plt_step_cnt > 30 * cpu_io_multi) then\r
+ global_step_cnt := global_step_cnt + 1;\r
+ end if;\r
+ end if;\r
+ plt_step_cnt := plt_step_cnt + 1;\r
+ \r
+ elsif (global_step_cnt = 2) then\r
+ --step1 = name table set.\r
+ if (nt_step_cnt = 0 * cpu_io_multi) then\r
+ --set vram addr 2005 (first row, 6th col)\r
+ io_out(16#2006#, 16#20#);\r
+ elsif (nt_step_cnt = 1 * cpu_io_multi) then\r
+ io_out(16#2006#, 16#06#);\r
+ elsif (nt_step_cnt = 2 * cpu_io_multi) then\r
+ --set name tbl data\r
+ --0x44, 45, 45 = DEE\r
+ io_out(16#2007#, 16#44#);\r
+ elsif (nt_step_cnt = 3 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#45#);\r
+ elsif (nt_step_cnt = 4 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#45#);\r
+\r
+\r
+ elsif (nt_step_cnt = 5 * cpu_io_multi) then\r
+ --set vram addr 23c1 (attribute)\r
+ io_out(16#2006#, 16#23#);\r
+ elsif (nt_step_cnt = 6 * cpu_io_multi) then\r
+ io_out(16#2006#, 16#c1#);\r
+ elsif (nt_step_cnt = 7 * cpu_io_multi) then\r
+ --attr=11011000\r
+ io_out(16#2007#, 16#d8#);\r
+\r
+\r
+ elsif (nt_step_cnt = 8 * cpu_io_multi) then\r
+ io_out(16#2006#, 16#20#);\r
+ elsif (nt_step_cnt = 9 * cpu_io_multi) then\r
+ io_out(16#2006#, 16#60#);\r
+\r
+ elsif (nt_step_cnt = 10 * cpu_io_multi) then\r
+ io_out(16#2007#, 48);\r
+ elsif (nt_step_cnt = 11 * cpu_io_multi) then\r
+ io_out(16#2007#, 49);\r
+ elsif (nt_step_cnt = 12 * cpu_io_multi) then\r
+ io_out(16#2007#, 50);\r
+ elsif (nt_step_cnt = 13 * cpu_io_multi) then\r
+ io_out(16#2007#, 51);\r
+ elsif (nt_step_cnt = 14 * cpu_io_multi) then\r
+ io_out(16#2007#, 52);\r
+ elsif (nt_step_cnt = 15 * cpu_io_multi) then\r
+ io_out(16#2007#, 53);\r
+ elsif (nt_step_cnt = 16 * cpu_io_multi) then\r
+ io_out(16#2007#, 54);\r
+ elsif (nt_step_cnt = 17 * cpu_io_multi) then\r
+ io_out(16#2007#, 55);\r
+ elsif (nt_step_cnt = 18 * cpu_io_multi) then\r
+ io_out(16#2007#, 56);\r
+\r
+ -- elsif (nt_step_cnt = 5 * cpu_io_multi) then\r
+ -- --set vram addr 21d1\r
+ -- io_out(16#2006#, 16#21#);\r
+ -- elsif (nt_step_cnt = 6 * cpu_io_multi) then\r
+ -- io_out(16#2006#, 16#E6#);\r
+ -- elsif (nt_step_cnt = 7 * cpu_io_multi) then\r
+ -- --msg=DEE TEST !!!\r
+ -- io_out(16#2007#, 16#44#);\r
+ -- elsif (nt_step_cnt = 8 * cpu_io_multi) then\r
+ -- io_out(16#2007#, 16#45#);\r
+ -- elsif (nt_step_cnt = 9 * cpu_io_multi) then\r
+ -- io_out(16#2007#, 16#45#);\r
+ -- elsif (nt_step_cnt = 10 * cpu_io_multi) then\r
+ -- io_out(16#2007#, 16#00#);\r
+ -- elsif (nt_step_cnt = 11 * cpu_io_multi) then\r
+ -- io_out(16#2007#, 16#54#);\r
+ -- elsif (nt_step_cnt = 12 * cpu_io_multi) then\r
+ -- io_out(16#2007#, 16#45#);\r
+ -- elsif (nt_step_cnt = 13 * cpu_io_multi) then\r
+ -- io_out(16#2007#, 16#53#);\r
+ -- elsif (nt_step_cnt = 14 * cpu_io_multi) then\r
+ -- io_out(16#2007#, 16#54#);\r
+ -- elsif (nt_step_cnt = 15 * cpu_io_multi) then\r
+ -- io_out(16#2007#, 16#21#);\r
+\r
+ --display test pattern\r
+ elsif (nt_step_cnt = 19 * cpu_io_multi) then\r
+ io_out(16#2006#, 16#20#);\r
+ elsif (nt_step_cnt = 20 * cpu_io_multi) then\r
+ io_out(16#2006#, 16#20#);\r
+ \r
+ elsif (nt_step_cnt = 21 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#01#);\r
+ elsif (nt_step_cnt = 22 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#02#);\r
+ elsif (nt_step_cnt = 23 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#03#);\r
+ elsif (nt_step_cnt = 24 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#04#);\r
+ elsif (nt_step_cnt = 25 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#05#);\r
+ elsif (nt_step_cnt = 26 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#06#);\r
+ elsif (nt_step_cnt = 27 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#07#);\r
+ elsif (nt_step_cnt = 28 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#08#);\r
+ elsif (nt_step_cnt = 29 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#09#);\r
+ elsif (nt_step_cnt = 30 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#0a#);\r
+ elsif (nt_step_cnt = 31 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#0b#);\r
+ elsif (nt_step_cnt = 32 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#0c#);\r
+ elsif (nt_step_cnt = 33 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#0d#);\r
+ elsif (nt_step_cnt = 34 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#0e#);\r
+ elsif (nt_step_cnt = 35 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#0f#);\r
+\r
+ elsif (nt_step_cnt = 36 * cpu_io_multi) then\r
+ io_out(16#2006#, 16#20#);\r
+ elsif (nt_step_cnt = 37 * cpu_io_multi) then\r
+ io_out(16#2006#, 16#40#);\r
+ \r
+ elsif (nt_step_cnt = 38 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#10#);\r
+ elsif (nt_step_cnt = 39 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#11#);\r
+ elsif (nt_step_cnt = 40 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#12#);\r
+ elsif (nt_step_cnt = 41 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#13#);\r
+ elsif (nt_step_cnt = 42 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#14#);\r
+ elsif (nt_step_cnt = 43 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#15#);\r
+ elsif (nt_step_cnt = 44 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#16#);\r
+ elsif (nt_step_cnt = 45 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#17#);\r
+ elsif (nt_step_cnt = 46 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#18#);\r
+ elsif (nt_step_cnt = 47 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#19#);\r
+ elsif (nt_step_cnt = 48 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#1a#);\r
+ elsif (nt_step_cnt = 49 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#1b#);\r
+ elsif (nt_step_cnt = 50 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#1c#);\r
+ elsif (nt_step_cnt = 51 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#1d#);\r
+ elsif (nt_step_cnt = 52 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#1e#);\r
+ elsif (nt_step_cnt = 53 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#1f#);\r
+\r
+ else\r
+ io_brk;\r
+ if (nt_step_cnt > 4 * cpu_io_multi) then\r
+ global_step_cnt := global_step_cnt + 1;\r
+ end if;\r
+ end if;\r
+ \r
+ nt_step_cnt := nt_step_cnt + 1;\r
+ \r
+ elsif (global_step_cnt = 3) then\r
+ --step2 = sprite set.\r
+ if (spr_step_cnt = 0) then\r
+ --set sprite addr=00 (first sprite)\r
+ io_out(16#2003#, 16#00#);\r
+ elsif (spr_step_cnt = 1 * cpu_io_multi) then\r
+ --set sprite data: y=02\r
+ io_out(16#2004#, 16#13#);\r
+ elsif (spr_step_cnt = 2 * cpu_io_multi) then\r
+ --tile=0x4d (ascii 'M')\r
+ io_out(16#2004#, 16#4d#);\r
+ elsif (spr_step_cnt = 3 * cpu_io_multi) then\r
+ --set sprite attr=03 (palette 03)\r
+ io_out(16#2004#, 16#01#);\r
+ elsif (spr_step_cnt = 4 * cpu_io_multi) then\r
+ --set sprite data: x=100\r
+ io_out(16#2004#, 16#64#);\r
+\r
+ elsif (spr_step_cnt = 5 * cpu_io_multi) then\r
+ --set sprite data: y=50\r
+ io_out(16#2004#, 16#32#);\r
+ elsif (spr_step_cnt = 6 * cpu_io_multi) then\r
+ --tile=0x4d (ascii 'O')\r
+ io_out(16#2004#, 16#4f#);\r
+ elsif (spr_step_cnt = 7 * cpu_io_multi) then\r
+ --set sprite attr=01\r
+ io_out(16#2004#, 16#01#);\r
+ elsif (spr_step_cnt = 8 * cpu_io_multi) then\r
+ --set sprite data: x=30\r
+ io_out(16#2004#, 16#1e#);\r
+\r
+ elsif (spr_step_cnt = 9 * cpu_io_multi) then\r
+ --set sprite data: y=60\r
+ io_out(16#2004#, 60);\r
+ elsif (spr_step_cnt = 10 * cpu_io_multi) then\r
+ --tile=0x4d (ascii 'P')\r
+ io_out(16#2004#, 16#50#);\r
+ elsif (spr_step_cnt = 11 * cpu_io_multi) then\r
+ --set sprite attr=01\r
+ io_out(16#2004#, 16#01#);\r
+ elsif (spr_step_cnt = 12 * cpu_io_multi) then\r
+ --set sprite data: x=33\r
+ io_out(16#2004#, 16#21#);\r
+\r
+ elsif (spr_step_cnt = 13 * cpu_io_multi) then\r
+ --set sprite data: y=61\r
+ io_out(16#2004#, 16#3d#);\r
+ elsif (spr_step_cnt = 14 * cpu_io_multi) then\r
+ --tile=0x4d (ascii 'Q')\r
+ io_out(16#2004#, 16#51#);\r
+ elsif (spr_step_cnt = 15 * cpu_io_multi) then\r
+ --set sprite attr=02\r
+ io_out(16#2004#, 16#02#);\r
+ elsif (spr_step_cnt = 16 * cpu_io_multi) then\r
+ --set sprite data: x=45\r
+ io_out(16#2004#, 45);\r
+\r
+ else\r
+ io_brk;\r
+ if (spr_step_cnt > 4 * cpu_io_multi) then\r
+ global_step_cnt := global_step_cnt + 1;\r
+ end if;\r
+ end if;\r
+ spr_step_cnt := spr_step_cnt + 1;\r
+\r
+ elsif (global_step_cnt = 4) then\r
+ --step3 = dma set.\r
+ for i in 0 to 64 loop\r
+ j := i * 4;\r
+ if (ch = 16#5b#) then\r
+ ch := 16#41#;\r
+ else\r
+ ch := 16#41# + i;\r
+ end if;\r
+\r
+ if (i < 64) then\r
+ --set dma value on the ram.\r
+ if (dma_step_cnt = (0 + j) * cpu_io_multi) then\r
+ io_out(16#0200# + j, i);\r
+ elsif (dma_step_cnt = (1 + j) * cpu_io_multi) then\r
+ io_out(16#0201# + j, ch);\r
+ elsif (dma_step_cnt = (2 + j) * cpu_io_multi) then\r
+ io_out(16#0202# + j, 16#01#);\r
+ elsif (dma_step_cnt = (3 + j) * cpu_io_multi) then\r
+ io_out(16#0203# + j, j);\r
+ elsif (dma_step_cnt = (0 + j) * cpu_io_multi + 1) or\r
+ (dma_step_cnt = (1 + j) * cpu_io_multi + 1) or\r
+ (dma_step_cnt = (2 + j) * cpu_io_multi + 1) or\r
+ (dma_step_cnt = (3 + j) * cpu_io_multi + 1) then\r
+ io_brk;\r
+ end if;\r
+ else\r
+ if (dma_step_cnt = (0 + j) * cpu_io_multi) then\r
+ --start dma\r
+ io_out(16#4014#, 16#02#);\r
+ elsif (dma_step_cnt = (0 + j) * cpu_io_multi + 1) then\r
+ io_brk;\r
+ elsif (dma_step_cnt = (0 + j) * cpu_io_multi + 2) then\r
+ io_brk;\r
+ global_step_cnt := global_step_cnt + 1;\r
+ end if;\r
+ end if;\r
+ end loop;\r
+ \r
+ dma_step_cnt := dma_step_cnt + 1;\r
+\r
+ elsif (global_step_cnt = 5) then\r
+ --final step = enable ppu.\r
+ if (enable_ppu_step_cnt = 0 * cpu_io_multi) then\r
+ --scroll reg set x.\r
+ io_out(16#2005#, 0);\r
+ elsif (enable_ppu_step_cnt = 1 * cpu_io_multi) then\r
+ --scroll reg set y.\r
+ io_out(16#2005#, 0);\r
+ elsif (enable_ppu_step_cnt = 2 * cpu_io_multi) then\r
+ --show bg\r
+ --PPUMASK=1e (show bg and sprite)\r
+ --PPUMASK=0e (show bg only)\r
+ io_out(16#2001#, 16#1e#);\r
+ elsif (enable_ppu_step_cnt = 3 * cpu_io_multi) then\r
+ --enable nmi\r
+ --PPUCTRL=80\r
+ io_out(16#2000#, 16#80#);\r
+ else\r
+ io_brk;\r
+ if (enable_ppu_step_cnt > 4 * cpu_io_multi) then\r
+ global_step_cnt := global_step_cnt + 1;\r
+ end if;\r
+ end if;\r
+ enable_ppu_step_cnt := enable_ppu_step_cnt + 1;\r
+\r
+ else\r
+ io_brk;\r
+ init_done := '1';\r
+ end if;\r
+ end if;--if (init_done = '0') then\r
+ else\r
+ r_nw <= 'Z';\r
+ addr <= (others => 'Z');\r
+ d_io <= (others => 'Z');\r
+ end if;--if (rdy = '1') then\r
+ end if; --if (rst_n = '0') then\r
+ end process;\r
+\r
+end rtl;\r
+\r
+\r
+\r
+\r
+\r
+\r
+-----------dummy prg rom\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+entity prg_rom is \r
+ generic (abus_size : integer := 15; dbus_size : integer := 8);\r
+ port (\r
+ clk : in std_logic;\r
+ ce_n : in std_logic; --active low.\r
+ addr : in std_logic_vector (abus_size - 1 downto 0);\r
+ data : out std_logic_vector (dbus_size - 1 downto 0)\r
+ );\r
+end prg_rom;\r
+architecture rtl of prg_rom is\r
+begin\r
+ data <= (others => 'Z');\r
+end rtl;\r
+\r
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