drm/amdgpu: use the BAR if possible in amdgpu_device_vram_access v2

This should speed up debugging VRAM access a lot.

v2: add HDP flush/invalidate

Unrevert: RAS issue at root of the issue has been addressed

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Jonathan Kim <Jonathan.Kim@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Kent Russell <kent.russell@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index caa38e7..bf302c7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -255,6 +255,32 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
        uint32_t hi = ~0;
        uint64_t last;
 
+
+#ifdef CONFIG_64BIT
+       last = min(pos + size, adev->gmc.visible_vram_size);
+       if (last > pos) {
+               void __iomem *addr = adev->mman.aper_base_kaddr + pos;
+               size_t count = last - pos;
+
+               if (write) {
+                       memcpy_toio(addr, buf, count);
+                       mb();
+                       amdgpu_asic_flush_hdp(adev, NULL);
+               } else {
+                       amdgpu_asic_invalidate_hdp(adev, NULL);
+                       mb();
+                       memcpy_fromio(buf, addr, count);
+               }
+
+               if (count == size)
+                       return;
+
+               pos += count;
+               buf += count / 4;
+               size -= count;
+       }
+#endif
+
        spin_lock_irqsave(&adev->mmio_idx_lock, flags);
        for (last = pos + size; pos < last; pos += 4) {
                uint32_t tmp = pos >> 31;