retval = 200;
#endif
break;
+ case SIG_DISPLAY_EXTRA_MODE: // FD04 bit 4, 3
+ retval = 0;
+#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
+ retval |= (kanjisub) ? 0x00 : 0x20;
+ retval |= (mode256k) ? 0x10 : 0x00;
+ retval |= (mode400line) ? 0x00 : 0x08;
+ retval |= (ram_protect) ? 0x00 : 0x04;
+#elif defined(_FM77L4)
+ retval |= (mode400line) ? 0x00 : 0x08;
+#endif
+ break;
case SIG_DISPLAY_X_WIDTH:
#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
retval = (mode320 || mode256k) ? 320 : 640;
int oldmode = display_mode;
kanjisub = ((data & 0x20) == 0) ? true : false;
# if defined(_FM77L4)
- stat_400linecard = ((data & 0x20) != 0) ? true : false;
+ stat_400linecard = ((data & 0x10) != 0) ? true : false;
mode400line = ((data & 0x08) != 0) ? false : true;
if(mode400line && stat_400linecard) {
display_mode = DISPLAY_MODE_8_400L_TEXT;
}
//fdc_motor = (fdc->read_signal(SIG_MB8877_MOTOR) != 0);
fdc_motor = false;
- fdc_cmd_type1 = false;
#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX) || \
defined(_FM77AV20) || defined(_FM77AV20EX)
if(!connect_fdc) return;
//irqreg_fdc = 0x00;
fdc_cmdreg = val;
- fdc_cmd_type1 = ((val & 0x80) == 0);
#if defined(HAS_DMA)
if(((fdc_cmdreg >= 0x80) && (fdc_cmdreg < 0xd0)) || (fdc_cmdreg >= 0xe0)) {
uint32_t words = dmac->read_signal(HD6844_WORDS_REG_0);
uint8_t FM7_MAINIO::get_fdc_motor(void)
{
uint8_t val = 0x3c; //0b01111100;
+ uint8_t drv;
+ bool bv;
+
if(!connect_fdc) return 0xff;
fdc_motor = (fdc->read_signal(SIG_MB8877_MOTOR) != 0) ? true : false;
- if(fdc_motor) val |= 0x80;
//fdc_drvsel = fdc->read_signal(SIG_MB8877_READ_DRIVE_REG);
+ drv = fdc_drvsel & 0x03;
val = val | (fdc_drvsel & 0x03);
#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX) || \
defined(_FM77AV20) || defined(_FM77AV20EX)
val = val | (fdc_drvsel & 0x40);
+ if((fdc_drvsel & 0x40) != 0) {
+ drv = fdc_drive_table[drv & 0x03];
+ }
#endif
+ fdc_motor = fdc_motor & (fdc->get_drive_type(drv) != DRIVE_TYPE_UNK);
+ if(fdc_motor) val |= 0x80;
#ifdef _FM7_FDC_DEBUG
this->out_debug_log(_T("FDC: Get motor/Drive: $%02x"), val);
#endif
} else {
irqreg_fdc &= 0xbf; //0b10111111;
}
+#if defined(_FM77_VARIANTS)
+ flag = flag & !(intmode_fdc);
+#endif
#if !defined(_FM8) // With FM8, $FD1F is alive and not do_irq(), Thanks to Anna_Wu.
irqstat_fdc = flag & !irqmask_mfd;
if(backup != irqstat_fdc) do_irq();
void FM7_MAINIO::set_fdc_motor(bool flag)
{
if(!connect_fdc) return;
+ uint8_t val;
fdc->write_signal(SIG_MB8877_MOTOR, flag ? 0x01 : 0x00, 0x01);
+ val = fdc_drvsel & 0x03;
+#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX) || \
+ defined(_FM77AV20) || defined(_FM77AV20EX)
+ if((fdc_drvsel & 0x40) == 0) {
+ val = fdc_drive_table[val & 0x03];
+ }
+#endif
fdc_motor = (fdc->read_signal(SIG_MB8877_MOTOR) != 0);
+ fdc_motor = fdc_motor & (fdc->get_drive_type(val) != DRIVE_TYPE_UNK);
}
+
--- /dev/null
+
+void FM7_MAINIO::reset_fdc_2HD(void)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return;
+ fdc_2HD_cmdreg = 0;
+ fdc_2HD_statreg = fdc_2HD->read_io8(0);
+ fdc_2HD_trackreg = fdc_2HD->read_io8(1);
+ fdc_2HD_sectreg = fdc_2HD->read_io8(2);
+ fdc_2HD_datareg = fdc_2HD->read_io8(3);
+ fdc_2HD_headreg = 0xfe | fdc_2HD->read_signal(SIG_MB8877_SIDEREG);
+ fdc_2HD_drvsel = 0x7c | fdc_2HD->read_signal(SIG_MB8877_DRIVEREG);
+ irqreg_fdc = 0x00; //0b00000000;
+ //fdc_2HD_motor = (fdc_2HD->read_signal(SIG_MB8877_MOTOR) != 0);
+ fdc_2HD_motor = false;
+
+ if(connect_fdc_2HD) {
+ fdc_2HD_reg_fd1e = 0x80;
+ for(int i = 0; i < 4; i++) {
+ fdc_2HD_drive_table[i] = (uint8_t)i;
+ fdc_2HD->set_drive_type(i, DRIVE_TYPE_2HD);
+ }
+ }
+ if(event_fdc_motor_2HD >= 0) cancel_event(this, event_fdc_motor_2HD);
+ event_fdc_motor_2HD = -1;
+ //irqstat_2HD_fdc = false;
+ //irqmask_2HD_mfd = true;
+ if(connect_fdc_2HD) {
+ set_fdc_motor_2HD(fdc_2HD_motor);
+ }
+#endif
+}
+
+void FM7_MAINIO::set_fdc_cmd_2HD(uint8_t val)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return;
+ //irqreg_fdc = 0x00;
+ fdc_2HD_cmdreg = val;
+#if 0
+#if defined(HAS_DMA)
+ if(((fdc_2HD_cmdreg >= 0x80) && (fdc_2HD_cmdreg < 0xd0)) || (fdc_2HD_cmdreg >= 0xe0)) {
+ uint32_t words = dmac->read_signal(HD6844_WORDS_REG_0);
+ if((words != 0) && (words < 0xffff) && (dmac->read_signal(HD6844_IS_TRANSFER_0) == 0)) {
+ dmac->write_signal(HD6844_SRC_FIXED_ADDR_CH0, 3, 0xffffffff);
+ dmac->write_signal(HD6844_TRANSFER_START, 0, 0xffffffff);
+ //this->out_debug_log(_T("FDC: Start DMA CMDREG=%02x CHRN=%02x %02x %02x * DRVSEL=%08x\n"),
+ // fdc_cmdreg, fdc_trackreg, fdc_headreg & 0x01, fdc_sectreg, fdc_drvsel);
+ }
+ }
+#endif
+#endif
+ fdc_2HD->write_io8(0, val & 0x00ff);
+#ifdef _FM7_FDC_DEBUG
+ this->out_debug_log(_T("FDC(2HD): CMD: $%02x"), fdc_2HD_cmdreg);
+#endif
+#endif
+}
+
+uint8_t FM7_MAINIO::get_fdc_stat(void)
+{
+#if defined(HAS_2HD)
+ uint32_t stat_backup = fdc_2HD_statreg;
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return 0xff;
+ fdc_2HD_statreg = fdc_2HD->read_io8(0);
+#ifdef _FM7_FDC_DEBUG
+ if(stat_backup != fdc_2HD_statreg) this->out_debug_log(_T("FDC(2HD): \nGet Stat(not busy): $%02x"), fdc_2HD_statreg);
+#endif
+ return fdc_2HD_statreg;
+#else
+ return 0xff;
+#endif
+}
+
+void FM7_MAINIO::set_fdc_track_2HD(uint8_t val)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return;
+ fdc_2HD_trackreg = val;
+ fdc_2HD->write_io8(1, val);
+#ifdef _FM7_FDC_DEBUG
+ this->out_debug_log(_T("FDC(2HD) : Set Track: %d"), val);
+#endif
+#endif
+}
+
+uint8_t FM7_MAINIO::get_fdc_track_2HD(void)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return 0xff;
+ fdc_2HD_trackreg = fdc_2HD->read_io8(1);
+ return fdc_2HD_trackreg;
+#else
+ return 0xff;
+#endif
+}
+
+void FM7_MAINIO::set_fdc_sector_2HD(uint8_t val)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return;
+ fdc_2HD_sectreg = val;
+ fdc_2HD->write_io8(2, val);
+#ifdef _FM7_FDC_DEBUG
+ this->out_debug_log(_T("FDC(2HD): Set Sector: $%02x"), val);
+#endif
+#endif
+}
+
+uint8_t FM7_MAINIO::get_fdc_sector_2HD(void)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return 0xff;
+ fdc_2HD_sectreg = fdc_2HD->read_io8(2);
+ return fdc_2HD_sectreg;
+#else
+ return 0xff;
+#endif
+}
+
+void FM7_MAINIO::set_fdc_data_2HD(uint8_t val)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return;
+ fdc_2HD_datareg = val;
+ fdc_2HD->write_io8(3, val & 0x00ff);
+#endif
+}
+
+uint8_t FM7_MAINIO::get_fdc_data(void)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return 0xff;
+ fdc_2HD_datareg = fdc_2HD->read_io8(3);
+
+ return fdc_2HD_datareg;
+#else
+ return 0xff;
+#endif
+}
+
+uint8_t FM7_MAINIO::get_fdc_motor_2HD(void)
+{
+#if defined(HAS_2HD)
+ uint8_t val = 0x3c; //0b01111100;
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return 0xff;
+ fdc_2HD_motor = (fdc_2HD->read_signal(SIG_MB8877_MOTOR) != 0) ? true : false;
+ fdc_2HD_motor = fdc_2HD_motor & (fdc_2HD->get_drive_type(fdc_2HD_drvsel & 3) != DRIVE_TYPE_UNK);
+ if(fdc_2HD_motor) val |= 0x80;
+ val = val | (fdc_2HD_drvsel & 0x03);
+ // OK?
+#ifdef _FM7_FDC_DEBUG
+ this->out_debug_log(_T("FDC(2HD): Get motor/Drive: $%02x"), val);
+#endif
+ return val;
+#else
+ return 0xff;
+#endif
+}
+
+void FM7_MAINIO::set_fdc_fd1c_2HD(uint8_t val)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return;
+ fdc_2HD_headreg = (val & 0x01) | 0xfe;
+ fdc_2HD->write_signal(SIG_MB8877_SIDEREG, val, 0x01);
+#ifdef _FM7_FDC_DEBUG
+ this->out_debug_log(_T("FDC(2HD): Set side/head: $%02x"), val);
+#endif
+#endif
+}
+
+uint8_t FM7_MAINIO::get_fdc_fd1c_2HD(void)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return 0xff;
+ //fdc_2HD_headreg = fdc_2HD->read_signal(SIG_MB8877_SIDEREG);
+ return fdc_2HD_headreg;
+#else
+ return 0xff;
+#endif
+}
+
+void FM7_MAINIO::set_fdc_fd1d_2HD(uint8_t val)
+{
+#if defined(HAS_2HD)
+ bool backup_motor = fdc_2HD_motor;
+ bool f;
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return;
+ if((val & 0x80) != 0) {
+ f = true;
+ } else {
+ f = false;
+ }
+
+ fdc_2HD->write_signal(SIG_MB8877_DRIVEREG, val, 0x03);
+ fdc_2HD_drvsel = val;
+
+ if(f != backup_motor) {
+ if(event_fdc_2HD_motor >= 0) cancel_event(this, event_fdc_2HD_motor);
+ // OK?
+ if(f) {
+ register_event(this, EVENT_FD_MOTOR_ON, 1000.0 * 300.0, false, &event_fdc_2HD_motor); // Motor ON After 0.3Sec.
+ } else {
+ register_event(this, EVENT_FD_MOTOR_OFF, 1000.0 * 50.0, false, &event_fdc_2HD_motor); // Motor OFF After 0.05Sec.
+ }
+ }
+#ifdef _FM7_FDC_DEBUG
+ this->out_debug_log(_T("FDC(2HD): Set Drive Select: $%02x"), val);
+#endif
+#endif
+}
+
+uint8_t FM7_MAINIO::get_fdc_fd1e_2HD(void)
+{
+ return 0xff;
+}
+
+void FM7_MAINIO::set_fdc_fd1e_2HD(uint8_t val)
+{
+}
+
+void FM7_MAINIO::set_irq_mfd_2HD(bool flag)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return;
+ //bool backup = irqstat_fdc_2HD;
+ bool backup = irqstat_fdc;
+ if(flag) {
+ irqreg_fdc |= 0x40; //0b01000000;
+ } else {
+ irqreg_fdc &= 0xbf; //0b10111111;
+ }
+# if defined(_FM77_VARIANTS) // With FM8, $FD1F is alive and not do_irq(), Thanks to Anna_Wu.
+ flag = flag & intmode_fdc;
+ irqstat_fdc = flag & !irqmask_mfd;
+ if(backup != irqstat_fdc) do_irq();
+# endif
+#endif
+ return;
+
+}
+
+void FM7_MAINIO::set_drq_mfd_2HD(bool flag)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return;
+ if(flag) {
+ irqreg_fdc_2HD |= 0x80;//0b10000000;
+ } else {
+ irqreg_fdc_2HD &= 0x7f; //0b01111111;
+ }
+# if defined(HAS_DMA)
+ if((dmac->read_signal(HD6844_IS_TRANSFER_0) != 0) && (flag)) {
+ dmac->write_signal(HD6844_DO_TRANSFER, 0x0, 0xffffffff);
+ }
+# endif
+#endif
+ return;
+}
+
+uint8_t FM7_MAINIO::fdc_getdrqirq_2HD(void)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return 0xff;
+ uint8_t val = irqreg_fdc_2HD | 0x3f;
+ return val;
+#else
+ return 0xff;
+#endif
+}
+
+void FM7_MAINIO::set_fdc_motor_2HD(bool flag)
+{
+#if defined(HAS_2HD)
+ if(!(connect_fdc_2HD) || (fdc_2HD == NULL)) return;
+ fdc_2HD->write_signal(SIG_MB8877_MOTOR, flag ? 0x01 : 0x00, 0x01);
+ fdc_2HD_motor = (fdc_2HD->read_signal(SIG_MB8877_MOTOR) != 0);
+ fdc_2HD_motor = fdc_2HD_motor & (fdc_2HD->get_drive_type(fdc_2HD_drvsel & 3) != DRIVE_TYPE_UNK);
+#endif
+}
# endif
#define MAX_DRIVE 4
#define CAPABLE_JCOMMCARD 1
+#define HAS_2HD
#elif defined(_FM77L4)
#define DEVICE_NAME "FUJITSU FM-77L4"
#elif defined(_FM77_VARIANTS)
stat_fdmode_2hd = false; // R/W : bit6, '0' = 2HD, '1' = 2DD. FM-77 Only.
stat_kanjirom = true; // R/W : bit5, '0' = sub, '1' = main. FM-77 Only.
- stat_400linecard = false;// R/W : bit4, '0' = connected. FM-77 Only.
#endif
firq_break_key = false; // bit1, ON = '0'.
firq_sub_attention = false; // bit0, ON = '0'.
event_fdc_motor = -1;
lpt_type = config.printer_type;
fdc_cmdreg = 0x00;
-
+#if defined(HAS_2HD)
+ event_fdc_motor_2HD = -1;
+#endif
#if defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
boot_ram = false;
# if defined(_FM77_VARIANTS)
stat_fdmode_2hd = false;
stat_kanjirom = true;
- stat_400linecard = false;
-# if defined(_FM77L4)
- stat_400linecard = true;
-# endif
# endif
#endif
#if defined(_FM77AV_VARIANTS)
val |= 0x01;
}
#if defined(_FM77_VARIANTS)
- if(stat_fdmode_2hd) val |= 0x40;
- if(stat_kanjirom) val |= 0x20;
- if(stat_400linecard) val |= 0x10;
- if((display->read_signal(SIG_DISPLAY_EXTRA_MODE) & 0x04) != 0x00) val |= 0x04;
+ if(!stat_fdmode_2hd) val |= 0x40;
+ if(stat_kanjirom) val |= 0x20;
+# if defined(_FM77L4)
+ val |= (display->read_signal(SIG_DISPLAY_EXTRA_MODE) & 0x18);
+# endif
#else
val |= 0x7c;
#endif
stat_kanjirom = ((val & 0x20) != 0);
#elif defined(_FM77_VARIANTS)
display->write_signal(SIG_DISPLAY_EXTRA_MODE, val, 0xff);
- stat_fdmode_2hd = ((val & 0x40) != 0);
+ stat_fdmode_2hd = ((val & 0x40) == 0);
stat_kanjirom = ((val & 0x20) != 0);
- stat_400linecard = ((val & 0x10) != 0);
+# if defined(_FM77L4)
+ display->write_signal(SIG_DISPLAY_EXTRA_MODE, val & 0x18, 0x18);
+# endif
#endif
}
retval = (uint32_t) get_extirq_fd17();
break;
#endif
+#if defined(HAS_2HD)
+ case 0x18: // FDC: STATUS
+ if(stat_fdmode_2hd) {
+ retval = (uint32_t) get_fdc_stat_2HD();
+ } else {
+ retval = (uint32_t) get_fdc_stat();
+ }
+ break;
+ //printf("FDC: READ STATUS %02x PC=%04x\n", retval, maincpu->get_pc());
+ break;
+ case 0x19: // FDC: Track
+ if(stat_fdmode_2hd) {
+ retval = (uint32_t) get_fdc_track_2HD();
+ } else {
+ retval = (uint32_t) get_fdc_track();
+ }
+ //printf("FDC: READ TRACK REG %02x\n", retval);
+ break;
+ case 0x1a: // FDC: Sector
+ if(stat_fdmode_2hd) {
+ retval = (uint32_t) get_fdc_sector_2HD();
+ } else {
+ retval = (uint32_t) get_fdc_sector();
+ }
+ //printf("FDC: READ SECTOR REG %02x\n", retval);
+ break;
+ case 0x1b: // FDC: Data
+ if(stat_fdmode_2hd) {
+ retval = (uint32_t) get_fdc_data_2HD();
+ } else {
+ retval = (uint32_t) get_fdc_data();
+ }
+ break;
+ case 0x1c:
+ if(stat_fdmode_2hd) {
+ retval = (uint32_t) get_fdc_fd1c_2HD();
+ } else {
+ retval = (uint32_t) get_fdc_fd1c();
+ }
+ //printf("FDC: READ HEAD REG %02x\n", retval);
+ break;
+ case 0x1d:
+ if(stat_fdmode_2hd) {
+ retval = (uint32_t) get_fdc_motor_2HD();
+ } else {
+ retval = (uint32_t) get_fdc_motor();
+ }
+ //printf("FDC: READ MOTOR REG %02x\n", retval);
+ break;
+ case 0x1e:
+ if(stat_fdmode_2hd) {
+ retval = (uint32_t) get_fdc_fd1e_2HD();
+ } else {
+ retval = (uint32_t) get_fdc_fd1e();
+ }
+ //printf("FDC: READ MOTOR REG %02x\n", retval);
+ break;
+ case 0x1f:
+ if(stat_fdmode_2hd) {
+ retval = (uint32_t) fdc_getdrqirq_2HD();
+ } else {
+ retval = (uint32_t) fdc_getdrqirq();
+ }
+ break;
+#else
case 0x18: // FDC: STATUS
- retval = (uint32_t) get_fdc_stat();
+ retval = (uint32_t) get_fdc_stat();
+ break;
//printf("FDC: READ STATUS %02x PC=%04x\n", retval, maincpu->get_pc());
break;
case 0x19: // FDC: Track
case 0x1f:
retval = (uint32_t) fdc_getdrqirq();
break;
+#endif
case 0x22: // Kanji ROM
retval = (uint32_t) read_kanjidata_left();
break;
set_ext_fd17((uint8_t)data);
break;
#endif
+#if defined(HAS_2HD)
+ case 0x18: // FDC: COMMAND
+ if(stat_fdmode_2hd) {
+ set_fdc_cmd_2HD((uint8_t)data);
+ } else {
+ set_fdc_cmd((uint8_t)data);
+ }
+ //printf("FDC: WRITE CMD %02x\n", data);
+ break;
+ case 0x19: // FDC: Track
+ if(stat_fdmode_2hd) {
+ set_fdc_track_2HD((uint8_t)data);
+ } else {
+ set_fdc_track((uint8_t)data);
+ }
+ //printf("FDC: WRITE TRACK REG %02x\n", data);
+ break;
+ case 0x1a: // FDC: Sector
+ if(stat_fdmode_2hd) {
+ set_fdc_sector_2HD((uint8_t)data);
+ } else {
+ set_fdc_sector((uint8_t)data);
+ }
+ //printf("FDC: WRITE SECTOR REG %02x\n", data);
+ break;
+ case 0x1b: // FDC: Data
+ if(stat_fdmode_2hd) {
+ set_fdc_data_2HD((uint8_t)data);
+ } else {
+ set_fdc_data((uint8_t)data);
+ }
+ break;
+ case 0x1c:
+ if(stat_fdmode_2hd) {
+ set_fdc_fd1c_2HD((uint8_t)data);
+ } else {
+ set_fdc_fd1c((uint8_t)data);
+ }
+ //printf("FDC: WRITE HEAD REG %02x\n", data);
+ break;
+ case 0x1d:
+ if(stat_fdmode_2hd) {
+ set_fdc_fd1d_2HD((uint8_t)data);
+ } else {
+ set_fdc_fd1d((uint8_t)data);
+ }
+ //printf("FDC: WRITE MOTOR REG %02x\n", data);
+ break;
+ case 0x1e:
+ if(stat_fdmode_2hd) {
+ set_fdc_fd1e_2HD((uint8_t)data);
+ } else {
+ set_fdc_fd1e((uint8_t)data);
+ }
+ break;
+ case 0x1f: // ??
+ return;
+ break;
+#else
case 0x18: // FDC: COMMAND
set_fdc_cmd((uint8_t)data);
//printf("FDC: WRITE CMD %02x\n", data);
case 0x1f: // ??
return;
break;
+#endif
case 0x20: // Kanji ROM
write_kanjiaddr_hi((uint8_t)data);
break;
set_fdc_motor(false);
event_fdc_motor = -1;
break;
+#if defined(HAS_2HD)
+ case EVENT_FD_MOTOR_ON_2HD:
+ set_fdc_motor_2HD(true);
+ event_fdc_motor_2HD = -1;
+ break;
+ case EVENT_FD_MOTOR_OFF_2HD:
+ set_fdc_motor_2HD(false);
+ event_fdc_motor_2HD = -1;
+ break;
+#endif
case EVENT_PRINTER_RESET_COMPLETED:
this->write_signals(&printer_reset_bus, 0x00);
break;
{
}
-#define STATE_VERSION 9
+#define STATE_VERSION 10
void FM7_MAINIO::save_state(FILEIO *state_fio)
{
int ch;
#if defined(_FM77_VARIANTS)
state_fio->FputBool(stat_fdmode_2hd);
state_fio->FputBool(stat_kanjirom);
- state_fio->FputBool(stat_400linecard);
#elif defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX) || \
defined(_FM77AV20) || defined(_FM77AV20EX) || defined(_FM77AV20SX)
state_fio->FputBool(stat_kanjirom);
state_fio->FputBool(midi_syndet);
state_fio->FputBool(midi_rxrdy);
state_fio->FputBool(midi_txrdy);
+#if defined(HAS_2HD)
+ state_fio->FputInt32_BE(event_fdc_motor_2HD);
+ state_fio->FputBool(connect_fdc_2HD);
+ state_fio->FputUint8(fdc_2HD_statreg);
+ state_fio->FputUint8(fdc_2HD_cmdreg);
+ state_fio->FputUint8(fdc_2HD_trackreg);
+ state_fio->FputUint8(fdc_2HD_sectreg);
+ state_fio->FputUint8(fdc_2HD_datareg);
+ state_fio->FputUint8(fdc_2HD_headreg);
+ state_fio->FputUint8(fdc_2HD_drvsel);
+ //state_fio->FputUint8(irqreg_fdc);
+ state_fio->FputBool(fdc_2HD_motor);
+ //state_fio->FputBool(irqstat_fdc);
+#endif
}
bool FM7_MAINIO::load_state(FILEIO *state_fio)
#if defined(_FM77_VARIANTS)
stat_fdmode_2hd = state_fio->FgetBool();
stat_kanjirom = state_fio->FgetBool();
- stat_400linecard = state_fio->FgetBool();
#elif defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX) || \
defined(_FM77AV20) || defined(_FM77AV20EX) || defined(_FM77AV20SX)
stat_kanjirom = state_fio->FgetBool();
midi_syndet = state_fio->FgetBool();
midi_rxrdy = state_fio->FgetBool();
midi_txrdy = state_fio->FgetBool();
+#if defined(HAS_2HD)
+ event_fdc_motor_2HD = state_fio->FgetInt32_BE();
+ connect_fdc_2HD = state_fio->FgetBool();
+ fdc_2HD_statreg = state_fio->FgetUint8();
+ fdc_2HD_cmdreg = state_fio->FgetUint8();
+ fdc_2HD_trackreg = state_fio->FgetUint8();
+ fdc_2HD_sectreg = state_fio->FgetUint8();
+ fdc_2HD_datareg =state_fio->FgetUint8();
+ fdc_2HD_headreg = state_fio->FgetUint8();
+ fdc_2HD_drvsel = state_fio->FgetUint8();
+ //state_fio->FputUint8(irqreg_fdc);
+ fdc_2HD_motor = state_fio->FgetBool();
+ //state_fio->FputBool(irqstat_fdc);
+#endif
if(version != STATE_VERSION) return false;
return true;
int event_beep;
int event_beep_oneshot;
int event_timerirq;
- int event_fdc_motor;
+ int event_fdc_motor;
+ int event_fdc_2HD_motor;
outputs_t clock_status;
outputs_t printer_reset_bus;
outputs_t printer_strobe_bus;
bool stat_kanjirom; // R/W : bit5, '0' = sub, '1' = main. FM-77 Only.
bool stat_400linecard;// R/W : bit4, '0' = connected. FM-77 Only.
//bool stat_400linemode; // R/W : bit3, '0' = 400line, '1' = 200line.
+#endif
+#if defined(HAS_2HD)
+ bool stat_fdmode_2hd; // R/W : bit6, '0' = 2HD, '1' = 2DD. FM-77 Only.
#endif
bool firq_break_key; // bit1, ON = '0'.
bool firq_sub_attention; // bit0, ON = '0'.
uint8_t fdc_statreg;
/* FD18 : W */
uint8_t fdc_cmdreg;
- bool fdc_cmd_type1;
/* FD19 : R/W */
uint8_t fdc_trackreg;
bool connect_kanjiroml2;
#endif
/* FD20, FD21 : R */
-
+
+ /* FD30 - FD36 : RW */
+ /* FD37 : R */
+ bool connect_fdc_2HD;
/* FD37 : W */
+ /* FD30 : R */
+ uint8_t fdc_2HD_statreg;
+ /* FD30 : W */
+ uint8_t fdc_2HD_cmdreg;
+
+ /* FD31 : R/W */
+ uint8_t fdc_2HD_trackreg;
+
+ /* FD32 : R/W */
+ uint8_t fdc_2HD_sectreg;
+
+ /* FD33 : R/W */
+ uint8_t fdc_2HD_datareg;
+
+ /* FD34 : R/W */
+ uint8_t fdc_2HD_headreg; // bit0, '0' = side0, '1' = side1
+
+ /* FD35 : R/W */
+ bool fdc_2HD_motor; // bit7 : '1' = ON, '0' = OFF
+ uint8_t fdc_2HD_drvsel; // bit 1-0
+ /* FD1F : R */
+ //uint8_t irqreg_2HD_fdc;
+ //bool irqstat_2HD_fdc;
#if defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
/* FD93: bit0 */
bool boot_ram;
void reset_fdc(void);
void set_fdc_motor(bool flag);
+ void reset_fdc_2HD(void);
+ void set_fdc_motor_2HD(bool flag);
+
void do_irq(void);
void set_irq_syndet(bool flag);
void set_irq_rxrdy(bool flag);
void set_fdc_misc(uint8_t val);
uint8_t get_fdc_misc(void);
+
+ uint8_t get_fdc_fd1c_2HD(void);
+ void set_fdc_fd1c_2HD(uint8_t val);
+ void set_fdc_fd1d_2HD(uint8_t val);
+
+ uint8_t get_fdc_fd1e_2HD(void);
+ void set_fdc_fd1e_2HD(uint8_t val);
+
+ uint8_t get_fdc_stat_2HD(void);
+ void set_fdc_cmd_2HD(uint8_t val);
+ uint8_t fdc_getdrqirq_2HD(void);
+
+ void set_fdc_track_2HD(uint8_t val);
+ uint8_t get_fdc_track_2HD(void);
+
+ uint8_t get_fdc_motor_2HD(void);
+ void set_fdc_sector_2HD(uint8_t val);
+ uint8_t get_fdc_sector_2HD(void);
+
+ void set_fdc_data_2HD(uint8_t val);
+ uint8_t get_fdc_data_2HD(void);
+
+ void set_fdc_misc_2HD(uint8_t val);
+ uint8_t get_fdc_misc_2HD(void);
+
/* Signal Handlers */
void set_beep_oneshot(void);
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