clk: meson-gxbb: expose UART clocks

Expose the clock ids of the three none AO uarts to the dt-bindings

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Helmut Klein <hgkr.klein@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[tidy the commit message to match similar change]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index e447f02..16ab5b2 100644 (file)
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -196,7 +196,7 @@
 /* #define CLKID_SAR_ADC */
 #define CLKID_SMART_CARD         24
 /* CLKID_RNG0 */
-#define CLKID_UART0              26
+/* CLKID_UART0 */
 #define CLKID_SDHC               27
 #define CLKID_STREAM             28
 #define CLKID_ASYNC_FIFO         29
@@ -218,7 +218,7 @@
 #define CLKID_ADC                45
 #define CLKID_BLKMV              46
 /* CLKID_AIU */
-#define CLKID_UART1              48
+/* CLKID_UART1 */
 #define CLKID_G2D                49
 /* CLKID_USB0 */
 /* CLKID_USB1 */
@@ -238,7 +238,7 @@
 /* CLKID_USB0_DDR_BRIDGE */
 #define CLKID_MMC_PCLK           66
 #define CLKID_DVIN               67
-#define CLKID_UART2              68
+/* CLKID_UART2 */
 /* #define CLKID_SANA */
 #define CLKID_VPU_INTR           70
 #define CLKID_SEC_AHB_AHB3_BRIDGE 71

diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index a1b2b50..98b39c2 100644 (file)
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -17,6 +17,7 @@
 #define CLKID_I2C              22
 #define CLKID_SAR_ADC          23
 #define CLKID_RNG0             25
+#define CLKID_UART0            26
 #define CLKID_SPI              34
 #define CLKID_ETH              36
 #define CLKID_AIU_GLUE         38
@@ -24,12 +25,14 @@
 #define CLKID_I2S_OUT          40
 #define CLKID_MIXER_IFACE      44
 #define CLKID_AIU              47
+#define CLKID_UART1            48
 #define CLKID_USB0             50
 #define CLKID_USB1             51
 #define CLKID_USB              55
 #define CLKID_HDMI_PCLK                63
 #define CLKID_USB1_DDR_BRIDGE  64
 #define CLKID_USB0_DDR_BRIDGE  65
+#define CLKID_UART2            68
 #define CLKID_SANA             69
 #define CLKID_GCLK_VENCI_INT0  77
 #define CLKID_AOCLK_GATE       80