radeonsi: don't set the CB clear color registers for 0/1 clear colors on Raven2

and add has_dcc_constant_encode.

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 3f53753..9026f61 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -212,8 +212,8 @@ static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
        }
 
        /* This doesn't need ELIMINATE_FAST_CLEAR.
-        * CB uses both the DCC clear codes and the CB clear color registers,
-        * so they must match.
+        * On chips predating Raven2, the DCC clear codes and the CB clear
+        * color registers must match.
         */
        *eliminate_needed = false;
 
@@ -548,6 +548,12 @@ static void si_do_fast_color_clear(struct si_context *sctx,
 
                *buffers &= ~clear_bit;
 
+               /* Chips with DCC constant encoding don't need to set the clear
+                * color registers for DCC clear values 0 and 1.
+                */
+               if (sctx->screen->has_dcc_constant_encode && !eliminate_needed)
+                       continue;
+
                if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
                        sctx->framebuffer.dirty_cbufs |= 1 << i;
                        si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 490a371..ba406be 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1029,6 +1029,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
                                           sscreen->info.family == CHIP_RAVEN;
        sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
                                        sscreen->info.family == CHIP_RAVEN;
+       sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2;
 
        if (sscreen->debug_flags & DBG(DPBB)) {
                sscreen->dpbb_allowed = true;

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 0807c8d..023e0f0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -445,6 +445,7 @@ struct si_screen {
        bool                            clear_db_cache_before_clear;
        bool                            has_msaa_sample_loc_bug;
        bool                            has_ls_vgpr_init_bug;
+       bool                            has_dcc_constant_encode;
        bool                            dpbb_allowed;
        bool                            dfsm_allowed;
        bool                            llvm_has_working_vgpr_indexing;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 0293bdf..e3b45fa 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -121,7 +121,7 @@ static void si_emit_cb_render_state(struct si_context *sctx)
                                S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
                                S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
                                S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
-                               S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->family == CHIP_RAVEN2));
+                               S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
        }
 
        /* RB+ register settings. */