arm64: dts: imx8: add conn lpcg clocks

Add conn lpcg clocks

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index e7c4425..c5ab23a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -4,15 +4,34 @@
  *     Dong Aisheng <aisheng.dong@nxp.com>
  */
 
+#include <dt-bindings/clock/imx8-lpcg.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+
 conn_subsys: bus@5b000000 {
        compatible = "simple-bus";
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
 
-       conn_lpcg: clock-controller@5b200000 {
-               reg = <0x5b200000 0xb0000>;
-               #clock-cells = <1>;
+       conn_axi_clk: clock-conn-axi {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <333333333>;
+               clock-output-names = "conn_axi_clk";
+       };
+
+       conn_ahb_clk: clock-conn-ahb {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <166666666>;
+               clock-output-names = "conn_ahb_clk";
+       };
+
+       conn_ipg_clk: clock-conn-ipg {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <83333333>;
+               clock-output-names = "conn_ipg_clk";
        };
 
        usdhc1: mmc@5b010000 {
@@ -83,4 +102,83 @@ conn_subsys: bus@5b000000 {
                power-domains = <&pd IMX_SC_R_ENET_1>;
                status = "disabled";
        };
+
+       /* LPCG clocks */
+       conn_lpcg: clock-controller-legacy@5b200000 {
+               reg = <0x5b200000 0xb0000>;
+               #clock-cells = <1>;
+       };
+
+       sdhc0_lpcg: clock-controller@5b200000 {
+               reg = <0x5b200000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&clk IMX_CONN_SDHC0_CLK>,
+                        <&conn_ipg_clk>, <&conn_axi_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
+                               <IMX_LPCG_CLK_5>;
+               clock-output-names = "sdhc0_lpcg_per_clk",
+                                    "sdhc0_lpcg_ipg_clk",
+                                    "sdhc0_lpcg_ahb_clk";
+               power-domains = <&pd IMX_SC_R_SDHC_0>;
+       };
+
+       sdhc1_lpcg: clock-controller@5b210000 {
+               reg = <0x5b210000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&clk IMX_CONN_SDHC1_CLK>,
+                        <&conn_ipg_clk>, <&conn_axi_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
+                               <IMX_LPCG_CLK_5>;
+               clock-output-names = "sdhc1_lpcg_per_clk",
+                                    "sdhc1_lpcg_ipg_clk",
+                                    "sdhc1_lpcg_ahb_clk";
+               power-domains = <&pd IMX_SC_R_SDHC_1>;
+       };
+
+       sdhc2_lpcg: clock-controller@5b220000 {
+               reg = <0x5b220000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&clk IMX_CONN_SDHC2_CLK>,
+                        <&conn_ipg_clk>, <&conn_axi_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
+                               <IMX_LPCG_CLK_5>;
+               clock-output-names = "sdhc2_lpcg_per_clk",
+                                    "sdhc2_lpcg_ipg_clk",
+                                    "sdhc2_lpcg_ahb_clk";
+               power-domains = <&pd IMX_SC_R_SDHC_2>;
+       };
+
+       enet0_lpcg: clock-controller@5b230000 {
+               reg = <0x5b230000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>,
+                        <&clk IMX_CONN_ENET0_ROOT_CLK>,
+                        <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+                               <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
+                               <IMX_LPCG_CLK_5>;
+               clock-output-names = "enet0_ipg_root_clk",
+                                    "enet0_tx_clk",
+                                    "enet0_ahb_clk",
+                                    "enet0_ipg_clk",
+                                    "enet0_ipg_s_clk";
+               power-domains = <&pd IMX_SC_R_ENET_0>;
+       };
+
+       enet1_lpcg: clock-controller@5b240000 {
+               reg = <0x5b240000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>,
+                        <&clk IMX_CONN_ENET1_ROOT_CLK>,
+                        <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+                               <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
+                               <IMX_LPCG_CLK_5>;
+               clock-output-names = "enet1_ipg_root_clk",
+                                    "enet1_tx_clk",
+                                    "enet1_ahb_clk",
+                                    "enet1_ipg_clk",
+                                    "enet1_ipg_s_clk";
+               power-domains = <&pd IMX_SC_R_ENET_1>;
+       };
 };