KVM: x86: hyper-v: Honor HV_MSR_SYNIC_AVAILABLE privilege bit

SynIC MSRs (HV_X64_MSR_SCONTROL, HV_X64_MSR_SVERSION, HV_X64_MSR_SIEFP,
HV_X64_MSR_SIMP, HV_X64_MSR_EOM, HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15)
are only available to guest when HV_MSR_SYNIC_AVAILABLE bit is exposed.

Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210521095204.2161214-12-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c
index 7ca7ea0..9d3aed3 100644 (file)
--- a/arch/x86/kvm/hyperv.c
+++ b/arch/x86/kvm/hyperv.c
@@ -1228,6 +1228,14 @@ static bool hv_check_msr_access(struct kvm_vcpu_hv *hv_vcpu, u32 msr)
        case HV_X64_MSR_REFERENCE_TSC:
                return hv_vcpu->cpuid_cache.features_eax &
                        HV_MSR_REFERENCE_TSC_AVAILABLE;
+       case HV_X64_MSR_SCONTROL:
+       case HV_X64_MSR_SVERSION:
+       case HV_X64_MSR_SIEFP:
+       case HV_X64_MSR_SIMP:
+       case HV_X64_MSR_EOM:
+       case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
+               return hv_vcpu->cpuid_cache.features_eax &
+                       HV_MSR_SYNIC_AVAILABLE;
        default:
                break;
        }