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drm/vc4: crtc: Clear the PixelValve FIFO during configuration
author
Maxime Ripard
<maxime@cerno.tech>
Thu, 3 Sep 2020 08:01:03 +0000
(10:01 +0200)
committer
Maxime Ripard
<maxime@cerno.tech>
Mon, 7 Sep 2020 16:04:17 +0000
(18:04 +0200)
Even though it's not really clear why we need to flush the PV FIFO during
the configuration even though we started by flushing it, experience shows
that without it we get a stale pixel stuck in the FIFO between the HVS and
the PV.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link:
https://patchwork.freedesktop.org/patch/msgid/ccd6269ba37b2f849ba6e62471c99bd93a4548a0.1599120059.git-series.maxime@cerno.tech
drivers/gpu/drm/vc4/vc4_crtc.c
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diff --git
a/drivers/gpu/drm/vc4/vc4_crtc.c
b/drivers/gpu/drm/vc4/vc4_crtc.c
index
73d9187
..
00b2c2b
100644
(file)
--- a/
drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/
drivers/gpu/drm/vc4/vc4_crtc.c
@@
-358,7
+358,7
@@
static void vc4_crtc_config_pv(struct drm_crtc *crtc)
if (is_dsi)
CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
- CRTC_WRITE(PV_CONTROL,
+ CRTC_WRITE(PV_CONTROL,
PV_CONTROL_FIFO_CLR |
vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |