--- /dev/null
+2001-09-17 Ben Elliston <bje@redhat.com>
+
+ * ms1-state-snapshot.exp: Run if $sidtarget(ms1) is set.
+
+2001-08-23 graydon hoare <graydon@redhat.com>
+
+ * ms1-state-snapshot.exp: New test.
+ * test-img.x: New binary file for test.
+
+2001-08-02 John Healy <jhealy@redhat.com>
+
+ * ms1-allinsn.exp: Load of basic-sid and run tests
+ using run-sid-tests-raw.
+
+2001-05-22 John Healy <jhealy@redhat.com>
+
+ * addinsns.s, ctinsn.s, intctrlinsns.s, ioinsns.s, logicalinsns.s,
+ memoryinsns.s, memoryinsns.s, mulinsns.s, shiftinsns.s, subinsns.s:
+ Added machine identification.
+ * ms1-allinsn.exp: Added --nosched to assembler flags.
+
+2001-05-17 John Healy <jhealy@redhat.com>
+
+ * ioinsns.s: Added tests for the rest of the io instructions.
+
+2001-05-14 John Healy <jhealy@redhat.com>
+
+ * ctinsns.s: Added test for brne instruction.
+
+2001-04-12 John Healy <jhealy@redhat.com>
+
+ * ctinsns.s: Updated expected value for pc offset from jal insn.
+
+2001-04-11 John Healy <jhealy@redhat.com>
+
+ * testutils.inc: Modified macros to use gloss-based syscalls and
+ to respect scheduling restrictions.
+ * addinsns.s, intctrlinsns.s, logicalinsns.s, memoryinsns.s,
+ mulinsns.s, shiftinsns.s, subinsns.s: Added .align directives to
+ .data sections and added nop's where necessary to obey the rules
+ of scheduling restrictions.
+
+2001-04-09 John Healy <jhealy@redhat.com>
+
+ * ctinsns.s: Adjusted test cases to test for delayed branching.
+ * testutils.inc: Modified macros to allow for delayed branching.
+
+2001-04-09 John Healy <jhealy@redhat.com>
+
+ * mulinsns.s: Added more tests.
+
+2001-04-06 John Healy <jhealy@redhat.com>
+
+ * ctinsns.s, intctrlinsns.s, ioinsns.s, logicalinsns.s
+ memoryinsns.s, mulinsns.s shiftinsns.s, subinsns.s: Renamed to have
+ better filename extension (.cgs changed to .s). New tests also added
+ to each file.
+ * addinsns.s: New file. Tests from add.cgs, addi.cgs and addui.cgs
+ grouped into addinsns.s.
+ * testutils.inc: Improved assertion and loading macros.
+
+2001-04-05 John Healy <jhealy@redhat.com>
+
+ * intctrlinsns.cgs: New tests added.
+
+2001-04-03 John Healy <jhealy@redhat.com>
+
+ * add.cgs: Improved tests.
+ * addi.cgs: New file.
+ * addiinsns.cgs: New file.
+ * addui.cgs: New file.
+ * ctinsns.cgs: New file.
+ * intctrlinsns.cgs: New file.
+ * ioinsns.cgs: New file.
+ * logicalinsns.cgs: New file.
+ * memoryinsns.cgs: New file.
+ * mulinsns.cgs: New file.
+ * shiftinsns.cgs: New file.
+ * subinsns.cgs: New file.
+ * testutils.inc: New file.
+
+2001-03-28 John Healy <jhealy@redhat.com>
+
+ * sidcomp.cgen-cpu.ms1/testutils.inc: Added support for
+ syscalls with up to three arguments.
+ * sidcomp.cgen-cpu.ms1/allinsn.exp: New file.
+ * sidcomp.cgen-cpu.ms1/add.cgs: New file.
+
--- /dev/null
+# mach(): ms1
+
+ .include "testutils.inc"
+ start
+
+ loadwl R7, value1
+ loadwl R8, value2
+
+testadd:
+ add R9, R7, R8
+ assertv R9, $1235
+
+testaddi:
+ addi R9, R8, #1 ; Positive immediate value
+ assertv R9, $1235
+
+testaddiagain:
+ addi R9, R9, #-1
+ assertv R9, $1234
+
+testaddionemoretime:
+ loadwl R7, value1 ; R7 contains 1.
+ addui R9, R0, #0 ; Clear R9: R9 contains 0.
+ addi R9, R0, #-3 ; Put expected result in R9.
+ addi R7, R7, #-4 ; R7 = R7 + -4 = -3
+ assertv R7,-3
+
+testaddui:
+ addui R9, R8, #1
+ assertv R9, $1235
+
+testadduiagain:
+ loadval R7, -6
+ addui R9, R7, #1
+ assertv R9, -5
+
+pass:
+ pass
+
+ .data
+ .align 4
+value1: .word 0x1
+value2: .word 0x1234
--- /dev/null
+# mach(): ms1
+
+ .include "testutils.inc"
+ start
+
+ loadwl R1, value1
+ loadwl R2, value2
+
+testbrlt:
+ assertv R14, 0
+ brlt R1, R2, testbrle
+ addi R14, R0, #1
+
+testbrle:
+ assertv R14, 1
+ brle R1,R2, testbrle2
+ addi R14, R14, #1
+
+testbrle2:
+ assertv R14, 2
+ brle R1, R1, testbreq
+ addi R14, R14, #1
+
+testbreq:
+ assertv R14, 3
+ breq R1, R1, testjmp
+ addi R14, R14, #1
+
+testjmp:
+ assertv R14, 4
+ jmp testjal
+ addi R14, R14, #1
+
+testjal:
+ assertv R14, 5
+ loadval R2, nobranchbrle
+ nop
+
+jallbl: jal R3, R2
+ addi R14, R14, #1
+
+nobranchbrle:
+ assertv R14, 6
+ assertv R3, (jallbl + 8) ; Did jal store the right return address?
+ brle R2, R1, fail
+ nop
+
+nobranchbrlt:
+ brlt R2, R1, fail
+ nop
+
+nobranchbreq:
+ breq R2, R1, fail
+ nop
+
+brne:
+ brne R0,R3,pass
+ nop
+ fail
+
+pass:
+ pass
+
+fail:
+ fail
+
+ .data
+ .align 4
+value1: .word 0001
+value2: .word 0x1234
--- /dev/null
+# mach(): ms1
+
+ .include "testutils.inc"
+ start
+
+ ; Interrupts should be disabled at startup.
+ si R4; Should issue error message.
+ ei
+ addi R1, R0, #75
+ si R4; Should be ok.
+ ei
+ di
+ si R4; Should issue error message.
+ loadval R6,pass
+ reti R6
+ add R0, R0, R0
+ fail
+
+pass:
+ pass
+
--- /dev/null
+# mach(): ms1
+
+ .include "testutils.inc"
+ start
+
+ loadwl R1, value1
+ loadwl R2, value2
+ loadwl R3, value3
+
+ outb R1, #0, R2
+ outh R2, #0, R2
+ outw R3, #0, R2
+ inb R1, R1, #0
+ assertv R1, 0
+ inh R2, R2, #0
+ assertv R2, 0
+ inw R3, R3, #0
+ assertv R3, 0
+
+pass:
+ pass
+
+ .data
+ .align 4
+value1: .word 0001
+value2: .word 0x1234
+value3: .word 0x5678
--- /dev/null
+# mach(): ms1
+
+ .include "testutils.inc"
+ start
+
+ loadval R6, value2 ; Use this throughout. To get at value1 or value2,
+ ; just use +/-1 offset. No need to waste another reg.
+
+ loadval R7, 0xffff ; To be used as a mask value throughout.
+ loadval R8, 0x0 ; To be used as a mask value throughout.
+ ldw R9, R6, #0 ; R9 should contain 0xf0f0f0f0 for use throughout.
+
+testand:
+ and R10, R9, R7
+ assertv R10, 0xf0f0
+
+testandi:
+ andi R10, R9, #$ffff
+ assertv R10, 0x0000f0f0
+
+testor:
+ or R10, R9, R7
+ assertv R10, 0xf0f0ffff
+
+testori:
+ ori R10, R9, #$ffff
+ assertv R10, 0xf0f0ffff
+
+testxor:
+ xor R10, R9, R7
+ assertv R10, 0xf0f00f0f
+
+testxori:
+ xori R10, R9, #$ffff
+ assertv R10, 0xf0f00f0f
+
+testnand:
+ nand R10, R9, R7
+ assertv R10, 0xffff0f0f
+
+testnandi:
+ nandi R10, R9, #$ffff
+ assertv R10, 0xffff0f0f
+
+testnor:
+ nor R10, R9, R7
+ ;assertv R10, 0x0f0f0000
+
+testnori:
+ nori R10, R9, #$ffff
+ assertv R10, 0x0f0f0000
+
+testxnor:
+ xnor R10, R9, R7
+ assertv R10, 0x0f0ff0f0
+
+testxnori:
+ xnori R10, R9, #$ffff
+ assertv R10, 0x0f0ff0f0
+
+testldui:
+ ldui R10,#$beef
+ assertv R10, 0xbeef0000
+
+pass:
+ pass
+
+
+ .data
+ .align 4
+value1: .word 0x1
+value2: .word 0xf0f0f0f0
--- /dev/null
+# mach(): ms1
+
+ .include "testutils.inc"
+ start
+
+ ; Test ldw with 0 offset.
+test1:
+ loadval R7, value1
+ ldw R8, R7, #0
+ assertv R8, 0x1234
+
+test2:
+ loadval R7, value2
+ ldw R8, R7, #0
+ assertv R8, 0x12345678
+
+test3:
+ loadval R7, value3
+ ldw R8, R7, #0;
+ assertv R8, 0xbeef0000
+
+ ; Test ldw with non-zero offsets.
+test4:
+ loadval R7, value1
+ ldw R8, R7, #4
+ assertv R8, 0x12345678
+
+test5:
+ loadval R7, value3
+ ldw R8, R7, #-4
+ assertv R8, 0x12345678
+
+ ; test stw with 0 offset
+test6:
+ loadval R7, value2 ; Where we want to store the new value.
+ loadval R8, $87654321 ; The new value: 0x87654321
+ stw R8, R7, #0 ; Use stw to fetch the word
+ loadwl R9, value2 ; Load it into R9 as well.
+ assertr R8, R9 ; Make sure they're equal.
+
+test7:
+ loadval R7, value1
+ loadval R8, $4321
+ stw R8, R7, #0
+ loadwl R9, value1
+ assertr R8, R9
+
+test8:
+ loadval R7, value3
+ loadval R8, $feed
+ stw R8, R7, #0
+ loadwl R9, value3
+ assertr R8, R9
+
+ ; test stw with non-zero offset
+test9:
+ loadval R7, value1
+ loadval R8, $deadbeef
+ stw R8, R7, #4
+ loadwl R9, value2
+ assertr R8, R9
+
+test10:
+ loadval R7, value2
+ loadval R8, $deadbeef
+ stw R8, R7, #-4
+ loadwl R9, value1
+ assertr R8, R9
+
+;; The ldb, ldbu and stb instructions are not really part of the
+;; mRISC-I architecture. They're part of the mRISC-II, but since
+;; the compiler has switches to generate/not generate them (in
+;; support of the future mRISC-II chip), we'll implement and
+;; test them so that the compiler developer can use them to
+;; test his code generation.
+
+test11:
+ loadval R7, value5
+ ldb R8, R7, #0 ; 0xffffffde (0xde sign extd) should be in R8.
+ assertv R8, 0xffffffde
+
+test12:
+ loadval R7, value6
+ ldb R8, R7, #-1
+ assertv R8, 0xffffffde
+
+test13:
+ loadval R7, value5
+ ldbu R8, R7, #0 ; 0xffffffde (0xde sign extd) should be in R8.
+ assertv R8, 0xde
+
+test14:
+ loadval R7, value6
+ ldbu R8, R7, #-1 ; 0xffffffde (0xde sign extd) should be in R8.
+ assertv R8, 0xde
+
+test15:
+ loadval R7, value5 ; Where we want to store the new value.
+ loadval R8, $fa ; The new value: 0xfa
+ stb R8, R7, #0 ; Store the new byte at value5
+ ldbu R9, R7,#0 ; Put the new byte into R9
+ assertr R8, R9 ; Make sure they're equal.
+
+test16:
+ loadval R7, value7 ; Where we want to store the new value.
+ loadval R8, $ce ; The new value: 0xce
+ stb R8, R7, #-1 ; Put the new byte at value6
+ loadval R9, value6 ; Get value 6 into R9
+ ldbu R10, R9,#0 ; Read the byte at value6 into R10
+ assertr R8, R10 ; Make sure they're equal.
+
+;; ldw and stw are for word access and ignore the two low-order bits so that they
+;; will only read a word from word-aligned addresses. Therefore, if addr1 is
+;; word-alligned, reading from/writing to addr1+[0,1,2,3] should produce the
+;; same results. The follow two tests check this behaviour.
+
+test17:
+ ; These should all load the same word.
+ loadval R7, value0
+ ldw R8, R7, #0 ; Load word at value0 into R8.
+ assertv R8, 0xaceface
+
+ ldw R8, R7, #1 ; Load word at value0 + 1 into R8.
+ assertv R8, 0xaceface
+
+ ldw R8, R7, #2 ; Load word at value0 + 2 into R8.
+ assertv R8, 0xaceface
+
+ ldw R8, R7, #3 ; Load word at value0 + 3 into R8.
+ assertv R8, 0xaceface
+
+test18:
+ ; These should all write to the same location.
+ loadval R7, value0
+ loadval R8, 0xfeedbeef
+ stw R8, R7, #0
+ loadwl R9, value0
+ assertv R9, 0xfeedbeef
+
+ loadval R8, 0xbadbed ; Change the value to be written to location value0
+ stw R8, R7, #1 ; Write to address value0 + 1.
+ loadwl R9, value0 ; Load word at value0 into R9.
+ assertv R9, 0xbadbed ; Make sure it's the same as the new value.
+
+ loadval R8, 0xfeedcab ; Change the value to be written to location value0
+ stw R8, R7, #2 ; Write to address value0 + 2.
+ loadwl R9, value0 ; Load word at address value0 into R9.
+ assertv R9, 0xfeedcab
+
+ loadval R8, 0xabcdef1 ; Change the value to be written to location value0
+ stw R8, R7, #2 ; Write to address value0 + 3.
+ loadwl R9, value0 ; Load word at address value0 into R9.
+ assertv R9, 0xabcdef1
+
+pass:
+ pass
+
+ .data
+ .align 4
+value0: .word 0xaceface
+value1: .word 0x1234
+value2: .word 0x12345678
+ .align 1
+value3: .byte 0xbe
+value4: .byte 0xef
+ .org 0x100
+ .align 1
+value5: .byte 0xde
+value6: .byte 0xed
+value7: .byte 0xaa
--- /dev/null
+# mRISC-I simulator testsuite.
+
+if {! $sidtarget(ms1)} { untested "hw-cpu-ms1 not available"; return }
+
+# Load a baseboard description for SID simulators.
+load_base_board_description "basic-sid"
+
+# load support procs (none yet)
+load_lib "cpudefs.exp"
+
+# all machines
+set all_machs "ms1"
+
+# Add --nosched to the flags to supress scheduling restrictions.
+set gas_flags "--gdwarf2 --nosched"
+
+# Run the tests
+run-sid-tests-raw ms1-elf ms1 $srcdir/sidcomp.cgen-cpu.ms1 "*.s" $gas_flags "" "" ms1-gloss.conf x
--- /dev/null
+# Testsuite for the CPU state snapshot and restoring.
+# Copyright (C) 2001 Red Hat
+
+if {! $sidtarget(ms1)} { untested "hw-cpu-ms1 not available"; return }
+
+set cpu "ms1"
+set filename "$srcdir/sidcomp.cgen-cpu.ms1/test-img.x"
+set conf_file "statesnap.conf"
+set start_insn 0x22d4
+
+
+set test "sid configuration"
+sid_config_component_etc_test_with_tracing "$conf_file" \
+ "load libcgencpu.la cgen_component_library" \
+ "hw-cpu-$cpu" \
+ "load libmemory.la mem_component_library
+load libloader.la loader_component_library
+
+new hw-memory-ram/rom-basic mem
+new sw-load-elf loader
+
+set loader file $filename
+connect-pin loader start-pc-set -> real-victim start-pc-set!
+connect-pin loader endian-set -> real-victim endian-set!
+connect-bus loader load-accessor-insn mem read-write-port
+connect-bus loader load-accessor-data mem read-write-port
+
+set mem size 0xffffff
+connect-bus real-victim data-memory mem read-write-port
+connect-bus real-victim insn-memory mem read-write-port
+
+relate tester loader loader
+"
+pass $test
+
+
+set test "sid startup"
+if [sid_start "$conf_file"] then { pass $test } else { fail $test ; return }
+
+
+set test "acquire loader load! pin"
+set load_pin [sid_cmd "sid::component::find_pin [sid_cmd {set relationships(loader)}] load!"]
+if {$load_pin != ""} { pass $test } else { fail $test }
+
+set test "acquire cpu reset! pin"
+set reset_pin [sid_cmd "sid::component::find_pin $victim reset!"]
+if {$reset_pin == ""} then { fail $test } else { pass $test }
+
+set test "acquire cpu step! pin"
+set step_pin [sid_cmd "sid::component::find_pin $victim step!"]
+if {$step_pin == ""} then { fail $test } else { pass $test }
+
+set test "acquire cpu start-pc-set! pin"
+set set_pc_pin [sid_cmd "sid::component::find_pin $victim start-pc-set!"]
+if {$set_pc_pin == ""} then { fail $test } else { pass $test }
+
+sid_cmd "sid::pin::driven_h4 $reset_pin 1"
+sid_cmd "sid::pin::driven_h4 $load_pin 1"
+
+# ignore any initialization in crt0; we're just doing simple memory writes
+set test "advancing to interesting position of test image"
+sid_cmd "sid::pin::driven_h4 $set_pc_pin $start_insn"
+set result [sid_cmd "sid::component::attribute_value $victim pc"]
+if {$result != $start_insn} then { fail $test } else { pass $test }
+
+
+# set our step-size to 100, to finish test quickly
+set test "set step-insn-count attribute"
+set result [sid_cmd "sid::component::set_attribute_value $victim step-insn-count 100"]
+if {$result == ""} then { fail $test } else { pass $test }
+
+# advance 100 insns into interesting stuff
+sid_cmd "sid::pin::driven_h4 $step_pin 1"
+
+# save state 1's PC
+set test "storing state 1's pc value"
+set first_pc [sid_cmd "sid::component::attribute_value $victim pc"]
+if {$first_pc == "" } then { fail $test } else { pass $test }
+
+
+# capture state
+set test "snapshot initial CPU state"
+set first_state [sid_cmd "sid::component::attribute_value $victim state-snapshot"]
+if {$first_state == ""} then { fail $test } else { pass $test }
+
+
+# advance through 100 more insns
+sid_cmd "sid::pin::driven_h4 $step_pin 1"
+
+
+# capture state
+set test "snapshot final CPU state"
+set second_state [sid_cmd "sid::component::attribute_value $victim state-snapshot"]
+if {$second_state == ""} then { fail $test } else { pass $test }
+
+
+# rewind to first capture
+set test "restore initial CPU state"
+set result [sid_cmd "sid::component::set_attribute_value $victim state-snapshot \"$first_state\""]
+if {$result == ""} then { fail $test } else { pass $test }
+
+
+# check that pc was reset
+set test "checking pc value rewound properly"
+set rewind_pc [sid_cmd "sid::component::attribute_value $victim pc"]
+if {$rewind_pc != $first_pc } then { fail $test } else { pass $test }
+
+
+# advance through second 100 insns again
+sid_cmd "sid::pin::driven_h4 $step_pin 1"
+
+# capture state
+set test "snapshot final CPU state again"
+set third_state [sid_cmd "sid::component::attribute_value $victim state-snapshot"]
+if {$third_state == ""} then { fail $test } else { pass $test }
+
+# compare states
+set test "comparing second and third states"
+if {$second_state != $third_state} then { fail $test } else { pass $test }
+
+
+set test "sid stop"
+if {[sid_stop]} { pass $test } else { fail $test ; return }
+
+# zap temp file if tests were successful
+global exit_status
+if {$exit_status == "0"} { file delete "$conf_file" }
--- /dev/null
+# mach(): ms1
+
+ .include "testutils.inc"
+ start
+
+test1: ; mul:
+ loadval R6, 0xfff
+ loadval R7, 0xfff
+ mul R8,R7,R6
+ assertv R8, 0xffe001
+
+test2:
+ ; mul: -1*1 = +1
+ loadval R6, 0x1
+ loadval R7, -1
+ mul R8,R7,R6
+ assertv R8, -1
+
+test3:
+ ; mul: -1*-1 = 1
+ loadval R6, -1
+ loadval R7, -1
+ mul R8,R7,R6
+ assertv R8, 1
+
+test4:
+ ; mul: 0x7fff * 0x7fff = 0x3fff0001
+ loadval R6, 0x7fff
+ loadval R7, 0x7fff
+ mul R8,R7,R6
+ assertv R8, 0x3fff0001
+
+
+test5: ; muli
+ loadval R6, 0xfff
+ muli R8,R6,#$fff
+ assertv R8, 0xffe001
+
+test6:
+ ; muli: -1*-1 = +1
+ loadval R6, -1
+ muli R8,R6, #-1
+ assertv R8, 1
+
+test7:
+ ; muli: -1*1 = -1
+ loadval R6, 1
+ muli R8,R6,#-1
+ assertv R8, -1
+
+test8:
+ ; muli: 0x7fff * 0x7fff = 0x3fff0001
+ loadval R6, 0x7fff
+ muli R8,R7,#$7fff
+ assertv R8, 0x3fff0001
+
+ pass
+
+ .data
+ .align 4
+value1:
+ .word 0xffff
+
--- /dev/null
+# mach(): ms1
+
+ .INCLUDE "testutils.inc"
+ start
+
+ loadwl R7 value2 ; Load 0x0f0f0f0f into R7
+ addui R8, R0, #4 ; Load the value we want to shift by (4) into R8.
+
+test1:
+ ; Test lsl - basic test.
+ lsl R7, R7, R8 ; Shift left by 4 bits: R7 should be 0xf0f0f0f0.
+
+ ; Put the expected result into R9.
+ loadwl R9, value3
+
+ ; Check to see if it's correct.
+ assertr R9,R7
+
+test2:
+ ; Test lsr - basic test.
+ lsr R7, R7, R8 ; Shift right by 4 bits: R7 should be 0x0f0f0f0f.
+
+ ; Put the expected value in R9
+ loadwl R9, value2
+
+ ; Check to see if it's correct.
+ assertr R9,R7
+
+test3:
+ ; Test lsli - basic test.
+ lsli R7, R7, #4 ; Shift left by 4 bits: R7 should be 0xf0f0f0f0.
+
+ ; Put the expected result into R9.
+ loadwl R9, value3
+
+ ; Check to see if it's correct.
+ assertr R9,R7
+
+test4:
+ ; Test lsri - basic test.
+ lsri R7, R7, #4 ; Shift right by 4 bits: R7 should be 0x0f0f0f0f.
+
+ ; Put the expected value in R9
+ loadwl R9, value2
+
+ ; Check to see if it's correct.
+ assertr R9,R7
+
+ ; Test asr.
+test5:
+ loadwl R7, value3
+ addui R8, R0, #16
+ asr R9, R7,R8
+ assertv R9, $fffff0f0
+
+test6:
+ loadwl R7, value2
+ addui R8, R0, #16
+ asr R9, R7,R8
+ assertv R9, $f0f
+
+ ; Test asri.
+test7:
+ loadwl R7, value3
+ asri R9, R7,#16
+ assertv R9, $fffff0f0
+
+test8:
+ loadwl R7, value2
+ asri R9, R7,#16
+ assertv R9, $f0f
+
+ ; Test shifts of 32 bits and make sure it results in 0.
+
+pass:
+ pass
+
+
+ .data
+ .align 4
+value1: .word 0x1
+value2: .word 0x0f0f0f0f
+value3: .word 0xf0f0f0f0
--- /dev/null
+# mach(): ms1
+
+ .include "testutils.inc"
+ start
+
+ loadwl R6, value1
+ loadwl R7, value2
+
+ assertv R6,$1
+
+test1: ; test sub
+ sub R8,R7,R6
+ assertv R8, $1233
+
+test2: ; test subi
+ subi R8, R8, #1
+ assertv R8, $1232
+
+
+test3: ; test subi for negative values
+ addui R8, R0, #0 ; Clear R8: R8 contains 0.
+ loadval R8, -4 ; Put expected result in R8.
+ loadwl R6, value1 ; R6 contains 1.
+ subi R6, R6, #5 ; R6 = R6 - 5 = -4.
+ assertv R6, -4
+ ei
+ addi R8, R0, #1 ; Put new expected value in R8.
+ subi R6, R6, #-5 ; R6 = R6 - -5 = 1.
+ ei
+ assertv R6, 1
+
+test4: ;test subui
+ loadwl R6 value2
+ subui R8, R6, #1
+ assertv R8, $1233
+
+test5: ; test subu
+ loadwl R6, value3 ; R6 should contain 0xfffffffe
+ loadval R7,1 ; R7 should contain 0xfffffffe
+ subu R8, R6, R7
+ assertv R8, 0xfffffffd
+
+test6: ; test subu
+ loadval R6, 0xfffffffe ; R6 should contain 0xfffffffe
+ loadval R7,1 ; R7 should contain 0xfffffffe
+ subu R8, R6, R7
+ assertv R8, 0xfffffffd
+
+test7: ; test sub with same case as subu
+ loadval R6, 0xfffffffe ; R6 should contain 0xfffffffe
+ loadval R7,1 ; R7 should contain 0xfffffffe
+ subu R8, R6, R7
+ assertv R8, -3
+
+pass:
+ pass
+
+ .data
+ .align 4
+value1: .word 0x0001
+value2: .word 0x1234
+value3: .word 0xfffffffe
--- /dev/null
+# -*- asm -*-
+
+# Make a system call with various numbers of arguments
+ .macro syscall0 call
+ addi r1,r0,\call
+ ;jal r14,r0
+ SI r14
+ ;add R0, R0, R0 ; Delay Slot.
+ nop
+ .endm
+ .macro syscall1 call arg1
+ addi r2,r0,\arg1
+ syscall0 \call
+ .endm
+ .macro syscall2 call arg1 arg2
+ addi r3,r0,\arg2
+ syscall1 \call,\arg1
+ .endm
+ .macro syscall3 call arg1 arg2 arg3
+ addi r4,r0,\arg3
+ syscall2 \call,\arg1,\arg2
+ .endm
+
+
+# Exit with return code
+ ;.macro exit rc
+ ; syscall1 #2,\rc
+ ;.endm
+
+# Fill r3/r4 here rather than via syscall3()
+ .macro write_stdout string,len
+ loadval r3,\string
+ loadval r4, \len
+ syscall1 #5, #1
+ .endm
+
+# Exit with return code
+ .macro exit rc
+ syscall1 #1,#\rc
+ .endm
+
+# Pass the test case
+ .macro pass
+ write_stdout passmsg,5
+ exit 0
+ .endm
+
+# Fail the testcase
+ .macro fail
+ write_stdout failmsg,5
+ exit 1
+ .endm
+
+# NOP
+ .macro nop
+ add R0, R0, R0
+ .endm
+
+# Assert that the contents of reg1 equals the contents of reg2.
+ .macro assertr reg1 reg2
+ breq \reg1, \reg2, exit\@
+ ;add R0, R0, R0 ; Delay slot.
+ nop
+ fail
+exit\@:
+ .endm
+
+# Assert that a register contains 0.
+ .macro assertz reg
+ breq \reg, R0, exit\@
+ ;add R0, R0, R0 ; Delay Slot.
+ nop
+ fail
+exit\@:
+ .endm
+
+# Assert that the contents of register reg match val.
+ .macro assertv reg val
+ addui R10,R0,#%hi16(\val)
+ lsli R10, R10, #16
+ addui R10, R10, #%lo16(\val)
+ breq \reg, R10, exit\@
+ ;dd R0, R0, R0 ; Delay Slot.
+ nop
+ fail
+exit\@:
+ .endm
+
+# Load the a word from memory into register reg.
+# This is not for putting the address of a label into
+ .macro loadwl reg label
+ addui R10, R0, #%hi16(\label)
+ lsli R10, R10, #16
+ addui R10, R10, #%lo16(\label) ; Address of label is now in R8.
+ ldw \reg, R10, #0 ; Put the word at label in reg.
+ nop
+ .endm
+
+# Load the a value into register reg. Note that if you want to
+# put the address of a label into a register, you use this.
+# Maybe I should duplicate this as loadaddr to avoid confusion.
+ .macro loadval reg val
+ addui R10, R0, #%hi16(\val)
+ lsli R10, R10, #16
+ addui R10, R10, #%lo16(\val) ; Address of label is now in R8.
+ addui \reg, R10, #0 ; Put the word at label in reg.
+ .endm
+
+
+
+
+
+# Canonical test case header
+ .macro start
+
+ .data
+ .align 4
+failmsg:
+ .ascii "fail\n"
+passmsg:
+ .ascii "pass\n"
+
+ .text
+ .global _start
+_start:
+ .endm
+
+
+
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