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KVM: PPC: Book3S: Define and use SRR1_MSR_BITS
authorNicholas Piggin <npiggin@gmail.com>
Wed, 2 Oct 2019 06:00:21 +0000 (16:00 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Tue, 22 Oct 2019 05:29:02 +0000 (16:29 +1100)
Acked-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
arch/powerpc/include/asm/reg.h
arch/powerpc/kvm/book3s.c
arch/powerpc/kvm/book3s_hv_nested.c

index b3cbb11..75c7e95 100644 (file)
 #define SPRN_USPRG7    0x107   /* SPRG7 userspace read */
 #define SPRN_SRR0      0x01A   /* Save/Restore Register 0 */
 #define SPRN_SRR1      0x01B   /* Save/Restore Register 1 */
+
+#ifdef CONFIG_PPC_BOOK3S
+/*
+ * Bits loaded from MSR upon interrupt.
+ * PPC (64-bit) bits 33-36,42-47 are interrupt dependent, the others are
+ * loaded from MSR. The exception is that SRESET and MCE do not always load
+ * bit 62 (RI) from MSR. Don't use PPC_BITMASK for this because 32-bit uses
+ * it.
+ */
+#define   SRR1_MSR_BITS                (~0x783f0000UL)
+#endif
+
 #define   SRR1_ISI_NOPT                0x40000000 /* ISI: Not found in hash */
 #define   SRR1_ISI_N_OR_G      0x10000000 /* ISI: Access is no-exec or G */
 #define   SRR1_ISI_PROT                0x08000000 /* ISI: Other protection fault */
index ec2547c..a2336c4 100644 (file)
@@ -136,7 +136,7 @@ void kvmppc_inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 flags)
 {
        kvmppc_unfixup_split_real(vcpu);
        kvmppc_set_srr0(vcpu, kvmppc_get_pc(vcpu));
-       kvmppc_set_srr1(vcpu, (kvmppc_get_msr(vcpu) & ~0x783f0000ul) | flags);
+       kvmppc_set_srr1(vcpu, (kvmppc_get_msr(vcpu) & SRR1_MSR_BITS) | flags);
        kvmppc_set_pc(vcpu, kvmppc_interrupt_offset(vcpu) + vec);
        vcpu->arch.mmu.reset_msr(vcpu);
 }
index cdf30c6..dc97e5b 100644 (file)
@@ -1186,7 +1186,7 @@ static int kvmhv_translate_addr_nested(struct kvm_vcpu *vcpu,
 forward_to_l1:
        vcpu->arch.fault_dsisr = flags;
        if (vcpu->arch.trap == BOOK3S_INTERRUPT_H_INST_STORAGE) {
-               vcpu->arch.shregs.msr &= ~0x783f0000ul;
+               vcpu->arch.shregs.msr &= SRR1_MSR_BITS;
                vcpu->arch.shregs.msr |= flags;
        }
        return RESUME_HOST;