net: hns3: some changes of MSI-X bits in PPU(RCB)

This patch modifies print message of rx_q_search_miss from error to dfx to
prevent misleading users, because this interrupt may occur if we receive
packets during initialization of HNS3 driver.
Otherwise, this patch masks 28th bit of PPU_MPF_ABNORMAL_SRC2 which is now
meaningless.

Signed-off-by: Weihang Li <liweihang@hisilicon.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
index ab9c5d5..3e0d6ee 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
@@ -1780,9 +1780,8 @@ static int hclge_handle_all_hw_msix_error(struct hclge_dev *hdev,
        status = le32_to_cpu(*(desc_data + 2)) &
                        HCLGE_PPU_MPF_INT_ST2_MSIX_MASK;
        if (status)
-               hclge_log_error(dev, "PPU_MPF_ABNORMAL_INT_ST2",
-                               &hclge_ppu_mpf_abnormal_int_st2[0],
-                               status, reset_requests);
+               dev_warn(dev, "PPU_MPF_ABNORMAL_INT_ST2 rx_q_search_miss found [dfx status=0x%x\n]",
+                        status);
 
        /* clear all main PF MSIx errors */
        ret = hclge_clear_hw_msix_error(hdev, desc, true, mpf_bd_num);

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
index d821a76..db318a4 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
@@ -81,7 +81,7 @@
 #define HCLGE_IGU_EGU_TNL_INT_MASK     GENMASK(5, 0)
 #define HCLGE_PPP_MPF_INT_ST3_MASK     GENMASK(5, 0)
 #define HCLGE_PPU_MPF_INT_ST3_MASK     GENMASK(7, 0)
-#define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK        GENMASK(29, 28)
+#define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK        BIT(29)
 #define HCLGE_PPU_PF_INT_RAS_MASK      0x18
 #define HCLGE_PPU_PF_INT_MSIX_MASK     0x26
 #define HCLGE_PPU_PF_OVER_8BD_ERR_MASK 0x01