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drm/amdgpu/vcn:Update SPG mode UVD status clear
authorJames Zhu <James.Zhu@amd.com>
Tue, 9 Oct 2018 21:06:56 +0000 (17:06 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 12 Oct 2018 17:55:59 +0000 (12:55 -0500)
Update Static Power Gate mode UVD status clear

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

index d8fe14d..bc64706 100644 (file)
@@ -883,9 +883,9 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
                UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
                ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
 
-       /* clear the bit 4 of VCN_STATUS */
-       WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
-                       ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+       /* clear the busy bit of UVD_STATUS */
+       tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
+       WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 
        /* force RBC into idle state */
        rb_bufsz = order_base_2(ring->ring_size);