extern struct nvkm_oclass *gm107_gr_oclass;
extern struct nvkm_oclass *gm204_gr_oclass;
extern struct nvkm_oclass *gm206_gr_oclass;
+extern struct nvkm_oclass *gm20b_gr_oclass;
#include <core/enum.h>
nvkm-y += nvkm/engine/gr/ctxgm107.o
nvkm-y += nvkm/engine/gr/ctxgm204.o
nvkm-y += nvkm/engine/gr/ctxgm206.o
+nvkm-y += nvkm/engine/gr/ctxgm20b.o
nvkm-y += nvkm/engine/gr/nv04.o
nvkm-y += nvkm/engine/gr/nv10.o
nvkm-y += nvkm/engine/gr/nv20.o
nvkm-y += nvkm/engine/gr/gm107.o
nvkm-y += nvkm/engine/gr/gm204.o
nvkm-y += nvkm/engine/gr/gm206.o
+nvkm-y += nvkm/engine/gr/gm20b.o
void gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *);
+void gm107_grctx_generate_bundle(struct gf100_grctx *);
+void gm107_grctx_generate_pagepool(struct gf100_grctx *);
+void gm107_grctx_generate_attrib(struct gf100_grctx *);
+
extern struct nvkm_oclass *gk110_grctx_oclass;
extern struct nvkm_oclass *gk110b_grctx_oclass;
extern struct nvkm_oclass *gk208_grctx_oclass;
extern struct nvkm_oclass *gm204_grctx_oclass;
void gm204_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
+void gm204_grctx_generate_tpcid(struct gf100_gr_priv *);
+void gm204_grctx_generate_405b60(struct gf100_gr_priv *);
extern struct nvkm_oclass *gm206_grctx_oclass;
+extern struct nvkm_oclass *gm20b_grctx_oclass;
/* context init value lists */
}
}
-static void
+void
gm107_grctx_generate_tpcid(struct gf100_gr_priv *priv)
{
int gpc, tpc, id;
* PGRAPH context implementation
******************************************************************************/
-static void
+void
gm204_grctx_generate_tpcid(struct gf100_gr_priv *priv)
{
int gpc, tpc, id;
nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */
}
-static void
+void
gm204_grctx_generate_405b60(struct gf100_gr_priv *priv)
{
const u32 dist_nr = DIV_ROUND_UP(priv->tpc_total, 4);
--- /dev/null
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include "ctxgf100.h"
+
+static void
+gm20b_grctx_generate_r406028(struct gf100_gr_priv *priv)
+{
+ u32 tpc_per_gpc = 0;
+ int i;
+
+ for (i = 0; i < priv->gpc_nr; i++)
+ tpc_per_gpc |= priv->tpc_nr[i] << (4 * i);
+
+ nv_wr32(priv, 0x406028, tpc_per_gpc);
+ nv_wr32(priv, 0x405870, tpc_per_gpc);
+}
+
+static void
+gm20b_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+{
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ int idle_timeout_save;
+ int i, tmp;
+
+ gf100_gr_mmio(priv, priv->fuc_sw_ctx);
+
+ gf100_gr_wait_idle(priv);
+
+ idle_timeout_save = nv_rd32(priv, 0x404154);
+ nv_wr32(priv, 0x404154, 0x00000000);
+
+ oclass->attrib(info);
+
+ oclass->unkn(priv);
+
+ gm204_grctx_generate_tpcid(priv);
+ gm20b_grctx_generate_r406028(priv);
+ gk104_grctx_generate_r418bb8(priv);
+
+ for (i = 0; i < 8; i++)
+ nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
+
+ nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
+
+ gk104_grctx_generate_rop_active_fbps(priv);
+ nv_wr32(priv, 0x408908, nv_rd32(priv, 0x410108) | 0x80000000);
+
+ for (tmp = 0, i = 0; i < priv->gpc_nr; i++)
+ tmp |= ((1 << priv->tpc_nr[i]) - 1) << (i * 4);
+ nv_wr32(priv, 0x4041c4, tmp);
+
+ gm204_grctx_generate_405b60(priv);
+
+ gf100_gr_wait_idle(priv);
+
+ nv_wr32(priv, 0x404154, idle_timeout_save);
+ gf100_gr_wait_idle(priv);
+
+ gf100_gr_mthd(priv, priv->fuc_method);
+ gf100_gr_wait_idle(priv);
+
+ gf100_gr_icmd(priv, priv->fuc_bundle);
+ oclass->pagepool(info);
+ oclass->bundle(info);
+}
+
+struct nvkm_oclass *
+gm20b_grctx_oclass = &(struct gf100_grctx_oclass) {
+ .base.handle = NV_ENGCTX(GR, 0x2b),
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
+ },
+ .main = gm20b_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .bundle = gm107_grctx_generate_bundle,
+ .bundle_size = 0x1800,
+ .bundle_min_gpm_fifo_depth = 0x182,
+ .bundle_token_limit = 0x1c0,
+ .pagepool = gm107_grctx_generate_pagepool,
+ .pagepool_size = 0x8000,
+ .attrib = gm107_grctx_generate_attrib,
+ .attrib_nr_max = 0x600,
+ .attrib_nr = 0x400,
+ .alpha_nr_max = 0xc00,
+ .alpha_nr = 0x800,
+}.base;
\ No newline at end of file
case 0xd7:
case 0xd9: /* 1/0/0/0, 1 */
case 0xea: /* gk20a */
+ case 0x12b: /* gm20b */
priv->magic_not_rop_nr = 0x01;
break;
}
struct nvkm_object **);
int gk104_gr_init(struct nvkm_object *);
+int gk20a_gr_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *data, u32 size,
+ struct nvkm_object **);
+void gk20a_gr_dtor(struct nvkm_object *);
+int gk20a_gr_init(struct nvkm_object *);
+
int gm204_gr_init(struct nvkm_object *);
extern struct nvkm_ofuncs gf100_fermi_ofuncs;
return pack;
}
-static int
+int
gk20a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
return 0;
}
-static void
+void
gk20a_gr_dtor(struct nvkm_object *object)
{
struct gf100_gr_priv *priv = (void *)object;
nv_wr32(priv, 0x419e4c, 0x7f);
}
-static int
+int
gk20a_gr_init(struct nvkm_object *object)
{
struct gk20a_gr_oclass *oclass = (void *)object->oclass;
--- /dev/null
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include "gk20a.h"
+#include "ctxgf100.h"
+
+#include <nvif/class.h>
+#include <subdev/timer.h>
+
+static struct nvkm_oclass
+gm20b_gr_sclass[] = {
+ { FERMI_TWOD_A, &nvkm_object_ofuncs },
+ { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs },
+ { MAXWELL_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { MAXWELL_COMPUTE_B, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
+ {}
+};
+
+static void
+gm20b_gr_init_gpc_mmu(struct gf100_gr_priv *priv)
+{
+ u32 val;
+
+ /* TODO this needs to be removed once secure boot works */
+ if (1) {
+ nv_wr32(priv, 0x100ce4, 0xffffffff);
+ }
+
+ /* TODO update once secure boot works */
+ val = nv_rd32(priv, 0x100c80);
+ val &= 0xf000087f;
+ nv_wr32(priv, 0x418880, val);
+ nv_wr32(priv, 0x418890, 0);
+ nv_wr32(priv, 0x418894, 0);
+
+ nv_wr32(priv, 0x4188b0, nv_rd32(priv, 0x100cc4));
+ nv_wr32(priv, 0x4188b4, nv_rd32(priv, 0x100cc8));
+ nv_wr32(priv, 0x4188b8, nv_rd32(priv, 0x100ccc));
+
+ nv_wr32(priv, 0x4188ac, nv_rd32(priv, 0x100800));
+}
+
+static void
+gm20b_gr_set_hww_esr_report_mask(struct gf100_gr_priv *priv)
+{
+ nv_wr32(priv, 0x419e44, 0xdffffe);
+ nv_wr32(priv, 0x419e4c, 0x5);
+}
+
+struct nvkm_oclass *
+gm20b_gr_oclass = &(struct gk20a_gr_oclass) {
+ .gf100 = {
+ .base.handle = NV_ENGINE(GR, 0x2b),
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk20a_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gk20a_gr_init,
+ .fini = _nvkm_gr_fini,
+ },
+ .cclass = &gm20b_grctx_oclass,
+ .sclass = gm20b_gr_sclass,
+ .ppc_nr = 1,
+ },
+ .init_gpc_mmu = gm20b_gr_init_gpc_mmu,
+ .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask,
+}.gf100.base;
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