drm/amd/display: Add pp_smu null pointer check

res_pool->pp_smu may be NULL. Check before use

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 2a807b9..8ee182b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1391,12 +1391,14 @@ void dcn_bw_update_from_pplib(struct dc *dc)
 
 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
 {
-       struct pp_smu_funcs_rv *pp = &dc->res_pool->pp_smu->rv_funcs;
+       struct pp_smu_funcs_rv *pp = NULL;
        struct pp_smu_wm_range_sets ranges = {0};
        int min_fclk_khz, min_dcfclk_khz, socclk_khz;
        const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
 
-       if (!pp->set_wm_ranges)
+       if (dc->res_pool->pp_smu)
+               pp = &dc->res_pool->pp_smu->rv_funcs;
+       if (!pp || !pp->set_wm_ranges)
                return;
 
        kernel_fpu_begin();

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
index 3b91505..2fb65d1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
@@ -171,7 +171,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
        struct pp_smu_display_requirement_rv *smu_req_cur =
                        &dc->res_pool->pp_smu_req;
        struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
-       struct pp_smu_funcs_rv *pp_smu = &dc->res_pool->pp_smu->rv_funcs;
+       struct pp_smu_funcs_rv *pp_smu = NULL;
        bool send_request_to_increase = false;
        bool send_request_to_lower = false;
        int display_count;
@@ -179,7 +179,8 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
        bool enter_display_off = false;
 
        display_count = get_active_display_cnt(dc, context);
-
+       if (dc->res_pool->pp_smu)
+               pp_smu = &dc->res_pool->pp_smu->rv_funcs;
        if (display_count == 0)
                enter_display_off = true;
 
@@ -189,7 +190,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
                 * if function pointer not set up, this message is
                 * sent as part of pplib_apply_display_requirements.
                 */
-               if (pp_smu->set_display_count)
+               if (pp_smu && pp_smu->set_display_count)
                        pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
 
                smu_req.display_count = display_count;
@@ -239,7 +240,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
         */
        if (send_request_to_increase) {
                /*use dcfclk to request voltage*/
-               if (pp_smu->set_hard_min_fclk_by_freq &&
+               if (pp_smu && pp_smu->set_hard_min_fclk_by_freq &&
                                pp_smu->set_hard_min_dcfclk_by_freq &&
                                pp_smu->set_min_deep_sleep_dcfclk) {
 
@@ -261,7 +262,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
 
        if (!send_request_to_increase && send_request_to_lower) {
                /*use dcfclk to request voltage*/
-               if (pp_smu->set_hard_min_fclk_by_freq &&
+               if (pp_smu && pp_smu->set_hard_min_fclk_by_freq &&
                                pp_smu->set_hard_min_dcfclk_by_freq &&
                                pp_smu->set_min_deep_sleep_dcfclk) {