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clk: renesas: r8a7796: Add PWM clock
authorRyo Kodama <ryo.kodama.vz@renesas.com>
Wed, 19 Apr 2017 17:46:38 +0000 (02:46 +0900)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 15 May 2017 07:46:31 +0000 (09:46 +0200)
This patch adds PWM clock for PWM.

Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
[geert: Correct parent clock]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a7796-cpg-mssr.c

index 5c95e63..ab8ad5e 100644 (file)
@@ -156,6 +156,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
        DEF_MOD("hscif1",                519,   R8A7796_CLK_S3D1),
        DEF_MOD("hscif0",                520,   R8A7796_CLK_S3D1),
        DEF_MOD("thermal",               522,   R8A7796_CLK_CP),
+       DEF_MOD("pwm",                   523,   R8A7796_CLK_S0D12),
        DEF_MOD("fcpvd2",                601,   R8A7796_CLK_S0D2),
        DEF_MOD("fcpvd1",                602,   R8A7796_CLK_S0D2),
        DEF_MOD("fcpvd0",                603,   R8A7796_CLK_S0D2),