drm/msm: Remember the state of A5XX hardware clock gating

Remember if the A5XX hardware clock gating is currently
enabled or disabled to avoid inadvertently enabling it.

Change-Id: Ic0dedbada3734a257ac966c041d06695f3521ad4
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 47f437f..e66079c 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -375,6 +375,7 @@ static const struct {
 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
 {
        struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+       struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
        unsigned int i;
 
        for (i = 0; i < ARRAY_SIZE(a5xx_hwcg); i++)
@@ -391,6 +392,11 @@ void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
 
        gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0);
        gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180);
+
+       if (state)
+               set_bit(A5XX_HWCG_ENABLED, &a5xx_gpu->flags);
+       else
+               clear_bit(A5XX_HWCG_ENABLED, &a5xx_gpu->flags);
 }
 
 static int a5xx_me_init(struct msm_gpu *gpu)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
index f8b0098..e637237 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
@@ -23,6 +23,7 @@
 
 enum {
        A5XX_ZAP_SHADER_LOADED = 1,
+       A5XX_HWCG_ENABLED = 2,
 };
 
 struct a5xx_gpu {