arm64: tegra: Enable DFLL clock on Jetson TX1

Enable DFLL clock for Jetson TX1 platform.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 37e3c46..9fad0d2 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -78,4 +78,25 @@
                        };
                };
        };
+
+       clock@70110000 {
+               status = "okay";
+
+               nvidia,cf = <6>;
+               nvidia,ci = <0>;
+               nvidia,cg = <2>;
+               nvidia,droop-ctrl = <0x00000f00>;
+               nvidia,force-mode = <1>;
+               nvidia,sample-rate = <25000>;
+
+               nvidia,pwm-min-microvolts = <708000>;
+               nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
+               nvidia,pwm-to-pmic;
+               nvidia,pwm-tristate-microvolts = <1000000>;
+               nvidia,pwm-voltage-step-microvolts = <19200>;
+
+               pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
+               pinctrl-0 = <&dvfs_pwm_active_state>;
+               pinctrl-1 = <&dvfs_pwm_inactive_state>;
+       };
 };