page boundary addr mode bug fixed, still dma doesn't work though...

diff --git a/de1_nes/cpu/alu.vhd b/de1_nes/cpu/alu.vhd
index 31c31e2..fb369ec 100644 (file)
--- a/de1_nes/cpu/alu.vhd
+++ b/de1_nes/cpu/alu.vhd
@@ -519,7 +519,7 @@ end procedure;
             al_reg_in <= addr_out;
             tmp_buf_we_n <= '0';
             tmp_reg_in <= ah_reg;
-        elsif (exec_cycle = T5) then
+        elsif (exec_cycle = T5 or exec_cycle = T0) then
             al_buf_we_n <= '1';
             tmp_buf_we_n <= '1';
             ea_carry <= '0';

diff --git a/de1_nes/cpu/decoder.vhd b/de1_nes/cpu/decoder.vhd
index 2529213..d15e04b 100644 (file)
--- a/de1_nes/cpu/decoder.vhd
+++ b/de1_nes/cpu/decoder.vhd
@@ -145,7 +145,7 @@ signal wk_acc_cmd         : std_logic_vector(3 downto 0);
 signal wk_x_cmd           : std_logic_vector(3 downto 0);
 signal wk_y_cmd           : std_logic_vector(3 downto 0);
 signal wk_stat_alu_we_n   : std_logic;
-signal old_ea_carry       : std_logic;
+signal ea_carry_reg       : std_logic;
 
 begin
 
@@ -154,8 +154,8 @@ begin
     pch_inc_reg : d_flip_flop_bit 
             port map(set_clk, '1', '1', '0', pch_inc_input, pch_inc_n);
 
-    old_ea_carry_reg : d_flip_flop_bit 
-            port map(set_clk, '1', '1', '0', ea_carry, old_ea_carry);
+    ea_carry_inst: d_flip_flop_bit 
+            port map(trig_clk, '1', '1', '0', ea_carry, ea_carry_reg);
 
     --acc,x,y next cycle is changed when it goes page across.
     --The conditional branch instructions all have the form xxy10000
@@ -515,7 +515,7 @@ begin
 
         wk_next_cycle <= T0;
         d_print("absx step 1");
-    elsif (exec_cycle = T0 and ea_carry = '1') then
+    elsif (exec_cycle = T0 and ea_carry_reg = '1') then
         --case page boundary crossed.
         --redo inst.
         d_print("absx 5 (page boudary crossed.)");
@@ -722,7 +722,7 @@ begin
         end if;
         wk_next_cycle <= T4;
     elsif exec_cycle = T4 then
-        if (ea_carry = '1') then
+        if (ea_carry_reg = '1') then
             pg_next_n <= '0';
         else
             pg_next_n <= '1';
@@ -778,7 +778,9 @@ begin
         --page handling.
         back_oe(wk_y_cmd, '1');
         indir_y_n <= '0';
-        if (old_ea_carry = '1') then
+        
+        --ea_carry reg is suspicious. timing is not garanteed...
+        if (ea_carry_reg = '1') then
             pg_next_n <= '0';
         else
             pg_next_n <= '1';
@@ -961,7 +963,7 @@ begin
     elsif exec_cycle = T4 then
         abs_latch_out;
         ea_x_out;
-        if (ea_carry = '1') then
+        if (ea_carry_reg = '1') then
             pg_next_n <= '0';
         else
             pg_next_n <= '1';

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
index 67fce61..8bb2e25 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
@@ -22,11 +22,11 @@ vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/address_decoder.vhd
 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/de1_nes.vhd}\r
 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/mem/prg_rom.vhd}\r
 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/mem/chr_rom.vhd}\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/vga.vhd}\r
 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/ppu.vhd}\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/render.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/vga_ppu.vhd}\r
 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/decoder.vhd}\r
 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/alu.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/dummy-mos6502.vhd}\r
 \r
 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/testbench_motones_sim.vhd}\r
 \r
@@ -39,59 +39,79 @@ add wave -label r_nw sim:/testbench_motones_sim/sim_board/r_nw;
 add wave -label cpu_clk sim:/testbench_motones_sim/sim_board/cpu_clk\r
 add wave -label addr -radix hex sim:/testbench_motones_sim/sim_board/addr\r
 add wave -label d_io -radix hex sim:/testbench_motones_sim/sim_board/d_io\r
-add wave -label instruction -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/instruction\r
-add wave -label int_d_bus -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/int_d_bus\r
-add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/exec_cycle\r
 \r
-add wave -divider regs\r
-add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/acc/q\r
-add wave -label status_val -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_register/status_val\r
-add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/sp/q\r
-add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/x/q\r
-add wave -label y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/y/q\r
+#add wave -label instruction -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/instruction\r
+#add wave -label int_d_bus -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/int_d_bus\r
+#add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/exec_cycle\r
+#\r
+#add wave -divider regs\r
+#add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/acc/q\r
+#add wave -label status_val -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_register/status_val\r
+#add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/sp/q\r
+#add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/x/q\r
+#add wave -label y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/y/q\r
 \r
 \r
 ##add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_reg\r
 \r
-add wave -divider ppu\r
+#add wave -divider ppu\r
+#\r
+#add wave  -label cpu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_addr\r
+#add wave  -label cpu_d -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_d\r
+#\r
+#add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
+#add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
+#\r
+#add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
+#\r
+#add wave -label ppu_ctl -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_ctrl\r
+#add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_mask\r
+#add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_status\r
+#\r
+#\r
+##add wave -label ppu_addr_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_cnt\r
+##add wave -label ppu_addr_we_n -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_we_n\r
+##add wave -label ppu_addr_in -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_in\r
+##add wave -label ppu_addr_inc1 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc1\r
+##add wave -label ppu_addr_inc32 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc32\r
+#\r
+#add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr\r
+#add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_data\r
+##add wave -label ppu_scr_x -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scrl_x\r
+##add wave -label ppu_scr_y -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scrl_y\r
+#\r
+####add wave sim:/testbench_motones_sim/sim_board/cpu_inst/*\r
+#\r
+#add wave -divider render\r
+#\r
+##add wave -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/pos_x \\r
+##sim:/testbench_motones_sim/sim_board/ppu_inst/pos_y \r
+#\r
+##add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/nes_r \\r
+##sim:/testbench_motones_sim/sim_board/ppu_inst/nes_g \\r
+##sim:/testbench_motones_sim/sim_board/ppu_inst/nes_b\r
+#\r
+#add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/h_sync_n\r
+#add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/v_sync_n\r
+\r
+\r
+\r
+add wave -divider apu\r
+\r
+add wave  -label cpu_addr sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n\r
+add wave  -label dma_next_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_next_status\r
+add wave  -label dma_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_status\r
+add wave  -label dma_cnt_ce sim:/testbench_motones_sim/sim_board/apu_inst/dma_cnt_ce\r
+add wave  -label rdy sim:/testbench_motones_sim/sim_board/apu_inst/rdy\r
+\r
+add wave  -label dma_write_we_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_write_we_n\r
+add wave  -label dma_addr -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_addr\r
+\r
+\r
+add wave  -label dma_start_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n\r
+add wave  -label dma_end_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_end_n\r
 \r
-add wave  -label cpu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_addr\r
-add wave  -label cpu_d -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_d\r
 \r
-add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
-add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
-\r
-add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
-\r
-add wave -label ppu_ctl -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_ctrl\r
-add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_mask\r
-add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_status\r
-\r
-\r
-#add wave -label ppu_addr_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_cnt\r
-#add wave -label ppu_addr_we_n -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_we_n\r
-#add wave -label ppu_addr_in -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_in\r
-#add wave -label ppu_addr_inc1 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc1\r
-#add wave -label ppu_addr_inc32 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc32\r
-\r
-add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr\r
-add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_data\r
-#add wave -label ppu_scr_x -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scrl_x\r
-#add wave -label ppu_scr_y -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scrl_y\r
-\r
-###add wave sim:/testbench_motones_sim/sim_board/cpu_inst/*\r
-\r
-add wave -divider render\r
-\r
-#add wave -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/pos_x \\r
-#sim:/testbench_motones_sim/sim_board/ppu_inst/pos_y \r
-\r
-#add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/nes_r \\r
-#sim:/testbench_motones_sim/sim_board/ppu_inst/nes_g \\r
-#sim:/testbench_motones_sim/sim_board/ppu_inst/nes_b\r
-\r
-add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/h_sync_n\r
-add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/v_sync_n\r
 \r
 view structure\r
 view signals\r
@@ -99,8 +119,5 @@ view signals
 run 8 us\r
 wave zoom full\r
 \r
-run 500 us\r
-wave zoom full\r
+run 430 us\r
 \r
-#run 1000 us\r
-#wave zoom full\r