protected:
bool canClobber(const SUnit *SU, const SUnit *Op);
- void AddPseudoTwoAddrDeps();
+ void AddPseudoTwoAddrDeps(const TargetInstrInfo *TII);
void PrescheduleNodesWithMultipleUses();
void CalculateSethiUllmanNumbers();
};
void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) {
SUnits = &sunits;
// Add pseudo dependency edges for two-address nodes.
- AddPseudoTwoAddrDeps();
+ AddPseudoTwoAddrDeps(TII);
// Reroute edges to nodes with multiple uses.
if (!TracksRegPressure)
PrescheduleNodesWithMultipleUses();
/// one that has a CopyToReg use (more likely to be a loop induction update).
/// If both are two-address, but one is commutable while the other is not
/// commutable, favor the one that's not commutable.
-void RegReductionPQBase::AddPseudoTwoAddrDeps() {
+void RegReductionPQBase::AddPseudoTwoAddrDeps(const TargetInstrInfo *TII) {
+ // If the graph contains any calls, disable this optimization.
+ // FIXME: This is a kludge to work around the fact that the artificial edges
+ // can combine with the way call sequences use physical register dependencies
+ // to model their resource usage to create unschedulable graphs.
+ for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
+ for (SDNode *Node = (*SUnits)[i].getNode(); Node; Node = Node->getGluedNode())
+ if (Node->isMachineOpcode() &&
+ Node->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode())
+ return;
+
for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
SUnit *SU = &(*SUnits)[i];
if (!SU->isTwoAddress)
; This testcase shouldn't need to spill the -1 value,
; so it should just use pcmpeqd to materialize an all-ones vector.
-; For i386, cp load of -1 are folded.
-; With -regalloc=greedy, the live range is split before spilling, so the first
-; pcmpeq doesn't get folded as a constant pool load.
-
-; I386-NOT: pcmpeqd
-; I386: orps LCPI0_2, %xmm
+; I386: pcmpeqd
; I386-NOT: pcmpeqd
-; I386: orps LCPI0_2, %xmm
; X86-64: pcmpeqd
; X86-64-NOT: pcmpeqd
--- /dev/null
+; RUN: llc -march=x86 -mcpu=pentium4 -mtriple=i686-none-linux < %s
+; PR11314
+
+; Make sure the scheduler's hack to insert artificial dependencies to optimize
+; two-address instruction scheduling doesn't interfere with the scheduler's
+; hack to model call sequences as artificial physical registers.
+
+define inreg { i64, i64 } @sscanf(i32 inreg %base.1.i) nounwind {
+entry:
+ %conv38.i92.i = sext i32 %base.1.i to i64
+ %rem.i93.i = urem i64 10, %conv38.i92.i
+ %div.i94.i = udiv i64 10, %conv38.i92.i
+ %a = insertvalue { i64, i64 } undef, i64 %rem.i93.i, 0
+ %b = insertvalue { i64, i64 } %a, i64 %div.i94.i, 1
+ ret { i64, i64 } %b
+}