drm/i915: Add two spaces before the SKL_DFSM registers

The next patches are going to touch this registers so here already
fixing it for older registers and make it consistent with most of
the other registers in this file.

Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191026001323.216052-1-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad646d7..2ddeeb2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7743,15 +7743,15 @@ enum {
 #define   CNL_DDI_CLOCK_REG_ACCESS_ON  (1 << 7)
 
 #define SKL_DFSM                       _MMIO(0x51000)
-#define SKL_DFSM_CDCLK_LIMIT_MASK      (3 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_675       (0 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_540       (1 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_450       (2 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_337_5     (3 << 23)
-#define SKL_DFSM_PIPE_A_DISABLE                (1 << 30)
-#define SKL_DFSM_PIPE_B_DISABLE                (1 << 21)
-#define SKL_DFSM_PIPE_C_DISABLE                (1 << 28)
-#define TGL_DFSM_PIPE_D_DISABLE                (1 << 22)
+#define   SKL_DFSM_CDCLK_LIMIT_MASK    (3 << 23)
+#define   SKL_DFSM_CDCLK_LIMIT_675     (0 << 23)
+#define   SKL_DFSM_CDCLK_LIMIT_540     (1 << 23)
+#define   SKL_DFSM_CDCLK_LIMIT_450     (2 << 23)
+#define   SKL_DFSM_CDCLK_LIMIT_337_5   (3 << 23)
+#define   SKL_DFSM_PIPE_A_DISABLE      (1 << 30)
+#define   SKL_DFSM_PIPE_B_DISABLE      (1 << 21)
+#define   SKL_DFSM_PIPE_C_DISABLE      (1 << 28)
+#define   TGL_DFSM_PIPE_D_DISABLE      (1 << 22)
 
 #define SKL_DSSM                               _MMIO(0x51004)
 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz                (1 << 31)