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MIPS: BMIPS: add clock controller nodes
authorJonas Gorski <jonas.gorski@gmail.com>
Thu, 2 May 2019 12:26:57 +0000 (14:26 +0200)
committerPaul Burton <paul.burton@mips.com>
Sun, 21 Jul 2019 22:23:24 +0000 (15:23 -0700)
Now that we have a driver for the clock controller, add nodes to allow
devices to make use of it.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
arch/mips/boot/dts/brcm/bcm3368.dtsi
arch/mips/boot/dts/brcm/bcm63268.dtsi
arch/mips/boot/dts/brcm/bcm6328.dtsi
arch/mips/boot/dts/brcm/bcm6358.dtsi
arch/mips/boot/dts/brcm/bcm6362.dtsi
arch/mips/boot/dts/brcm/bcm6368.dtsi

index 7a3e5c8..69cbef4 100644 (file)
                compatible = "simple-bus";
                ranges;
 
-               periph_cntl: syscon@fff8c000 {
+               clkctl: clock-controller@fff8c004 {
+                       compatible = "brcm,bcm3368-clocks";
+                       reg = <0xfff8c004 0x4>;
+                       #clock-cells = <1>;
+               };
+
+               periph_cntl: syscon@fff8c008 {
                        compatible = "syscon";
-                       reg = <0xfff8c000 0xc>;
+                       reg = <0xfff8c000 0x4>;
                        native-endian;
                };
 
                reboot: syscon-reboot@fff8c008 {
                        compatible = "syscon-reboot";
                        regmap = <&periph_cntl>;
-                       offset = <0x8>;
+                       offset = <0x0>;
                        mask = <0x1>;
                };
 
index 58790b1..beec241 100644 (file)
                compatible = "simple-bus";
                ranges;
 
-               periph_cntl: syscon@10000000 {
+               clkctl: clock-controller@10000004 {
+                       compatible = "brcm,bcm63268-clocks";
+                       reg = <0x10000004 0x4>;
+                       #clock-cells = <1>;
+               };
+
+               periph_cntl: syscon@10000008 {
                        compatible = "syscon";
-                       reg = <0x10000000 0x14>;
+                       reg = <0x10000000 0xc>;
                        native-endian;
                };
 
                reboot: syscon-reboot@10000008 {
                        compatible = "syscon-reboot";
                        regmap = <&periph_cntl>;
-                       offset = <0x8>;
+                       offset = <0x0>;
                        mask = <0x1>;
                };
 
index bf6716a..af860d0 100644 (file)
                compatible = "simple-bus";
                ranges;
 
+               clkctl: clock-controller@10000004 {
+                       compatible = "brcm,bcm6328-clocks";
+                       reg = <0x10000004 0x4>;
+                       #clock-cells = <1>;
+               };
+
                periph_intc: interrupt-controller@10000020 {
                        compatible = "brcm,bcm6345-l1-intc";
                        reg = <0x10000020 0x10>,
index 26ddae5..f21176c 100644 (file)
                compatible = "simple-bus";
                ranges;
 
-               periph_cntl: syscon@fffe0000 {
+               clkctl: clock-controller@fffe0004 {
+                       compatible = "brcm,bcm6358-clocks";
+                       reg = <0xfffe0004 0x4>;
+                       #clock-cells = <1>;
+               };
+
+               periph_cntl: syscon@fffe0008 {
                        compatible = "syscon";
-                       reg = <0xfffe0000 0xc>;
+                       reg = <0xfffe0000 0x4>;
                        native-endian;
                };
 
                reboot: syscon-reboot@fffe0008 {
                        compatible = "syscon-reboot";
                        regmap = <&periph_cntl>;
-                       offset = <0x8>;
+                       offset = <0x0>;
                        mask = <0x1>;
                };
 
index c387793..8ae6981 100644 (file)
                compatible = "simple-bus";
                ranges;
 
-               periph_cntl: syscon@10000000 {
+               clkctl: clock-controller@10000004 {
+                       compatible = "brcm,bcm6362-clocks";
+                       reg = <0x10000004 0x4>;
+                       #clock-cells = <1>;
+               };
+
+               periph_cntl: syscon@10000008 {
                        compatible = "syscon";
-                       reg = <0x10000000 0x14>;
+                       reg = <0x10000000 0xc>;
                        native-endian;
                };
 
                reboot: syscon-reboot@10000008 {
                        compatible = "syscon-reboot";
                        regmap = <&periph_cntl>;
-                       offset = <0x8>;
+                       offset = <0x0>;
                        mask = <0x1>;
                };
 
index e116a38..449c167 100644 (file)
                compatible = "simple-bus";
                ranges;
 
-               periph_cntl: syscon@10000000 {
+               clkctl: clock-controller@10000004 {
+                       compatible = "brcm,bcm6368-clocks";
+                       reg = <0x10000004 0x4>;
+                       #clock-cells = <1>;
+               };
+
+               periph_cntl: syscon@100000008 {
                        compatible = "syscon";
-                       reg = <0x10000000 0x14>;
+                       reg = <0x10000000 0xc>;
                        native-endian;
                };
 
                reboot: syscon-reboot@10000008 {
                        compatible = "syscon-reboot";
                        regmap = <&periph_cntl>;
-                       offset = <0x8>;
+                       offset = <0x0>;
                        mask = <0x1>;
                };