radeonsi: remove the tf_ring state, add the registers to init_config

One less state to worry about.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index c3f96e0..f6f7753 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -49,7 +49,6 @@ static void si_destroy_context(struct pipe_context *context)
        sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
 
        si_pm4_free_state(sctx, sctx->init_config, ~0);
-       si_pm4_delete_state(sctx, tf_ring, sctx->tf_state);
        for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
                si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
 

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 687114b..9fe1798 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -203,7 +203,6 @@ struct si_context {
        struct si_pm4_state     *vgt_shader_config[4];
        struct pipe_resource    *esgs_ring;
        struct pipe_resource    *gsvs_ring;
-       struct si_pm4_state     *tf_state;
        struct pipe_resource    *tf_ring;
 
        LLVMTargetMachineRef            tm;

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index cd01074..8cf308d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -96,7 +96,6 @@ union si_state {
                struct si_pm4_state             *hs;
                struct si_pm4_state             *es;
                struct si_pm4_state             *gs;
-               struct si_pm4_state             *tf_ring;
                struct si_pm4_state             *vgt_shader_config;
                struct si_pm4_state             *vs;
                struct si_pm4_state             *ps;

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 43dbe03..8ef02c4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1255,8 +1255,7 @@ static void si_update_spi_tmpring_size(struct si_context *sctx)
 
 static void si_init_tess_factor_ring(struct si_context *sctx)
 {
-       assert(!sctx->tf_state);
-       sctx->tf_state = CALLOC_STRUCT(si_pm4_state);
+       assert(!sctx->tf_ring);
 
        sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
                                           PIPE_USAGE_DEFAULT,
@@ -1265,26 +1264,28 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
                             sctx->tf_ring->width0, fui(0), false);
        assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
 
+       /* Append these registers to the init config state. */
        if (sctx->b.chip_class >= CIK) {
-               si_pm4_set_reg(sctx->tf_state, R_030938_VGT_TF_RING_SIZE,
+               si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
                               S_030938_SIZE(sctx->tf_ring->width0 / 4));
-               si_pm4_set_reg(sctx->tf_state, R_030940_VGT_TF_MEMORY_BASE,
+               si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
                               r600_resource(sctx->tf_ring)->gpu_address >> 8);
        } else {
-               si_pm4_set_reg(sctx->tf_state, R_008988_VGT_TF_RING_SIZE,
+               si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
                               S_008988_SIZE(sctx->tf_ring->width0 / 4));
-               si_pm4_set_reg(sctx->tf_state, R_0089B8_VGT_TF_MEMORY_BASE,
+               si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
                               r600_resource(sctx->tf_ring)->gpu_address >> 8);
        }
-       si_pm4_add_bo(sctx->tf_state, r600_resource(sctx->tf_ring),
-                     RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
-       si_pm4_bind_state(sctx, tf_ring, sctx->tf_state);
+
+       /* Flush the context to re-emit the init_config state.
+        * This is done only once in a lifetime of a context.
+        */
+       sctx->b.initial_gfx_cs_size = 0; /* force flush */
+       si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
 
        si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
                           SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
                           sctx->tf_ring->width0, false, false, 0, 0, 0);
-
-       sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
 }
 
 /**
@@ -1373,7 +1374,7 @@ void si_update_shaders(struct si_context *sctx)
 
        /* Update stages before GS. */
        if (sctx->tes_shader) {
-               if (!sctx->tf_state)
+               if (!sctx->tf_ring)
                        si_init_tess_factor_ring(sctx);
 
                /* VS as LS */