constant dsize : integer := 8;
constant OAM_DMA : std_logic_vector(4 downto 0) := "10100";
+constant OAM_JP1 : std_logic_vector(4 downto 0) := "10110";
+constant OAM_JP2 : std_logic_vector(4 downto 0) := "10111";
--oamaddr=0x2003
constant OAMADDR : std_logic_vector(15 downto 0) := "0010000000000011";
reg_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d)
begin
if (rst_n = '1' and ce_n = '0') then
- if(cpu_addr(4 downto 0) = OAM_DMA and r_nw = '0') then
- dma_start_n <= '0';
- else
- dma_start_n <= '1';
+ if (r_nw = '0') then
+ --apu write
+ if (cpu_addr(4 downto 0) = OAM_DMA) then
+ dma_start_n <= '0';
+ else
+ dma_start_n <= '1';
+ end if;
+ elsif (r_nw = '1') then
+ --apu read
+ if (cpu_addr(4 downto 0) = OAM_JP1) then
+ cpu_d <= (others => '0');
+ elsif (cpu_addr(4 downto 0) = OAM_JP2) then
+ cpu_d <= (others => '0');
+ else
+ --return dummy zero vale.
+ cpu_d <= (others => '0');
+ end if;
end if;
else
+ cpu_d <= (others => 'Z');
dma_start_n <= '1';
end if; --if (rst_n = '1' and ce_n = '0')
end process;
elsif (dma_status = DMA_ST_SETUP) then
cpu_addr <= OAMADDR;
cpu_d <= (others => '0');
+ r_nw <= '0';
dma_next_status <= DMA_ST_PROCESS;
elsif (dma_status = DMA_ST_PROCESS) then
if (dma_addr(dsize - 1 downto 0) = "11111111" and dma_cnt_ce_n(0) = '1') then