Change-Id: Ic2b1f4775d24a1cf729a0dde1c8d2e1d6a85ef95

diff --git a/VGADisplay/Verilog/tb.v b/VGADisplay/Verilog/tb.v
new file mode 100644 (file)
index 0000000..0b0147a
--- /dev/null
+++ b/VGADisplay/Verilog/tb.v
@@ -0,0 +1,67 @@
+`timescale     1ns / 1ps
+
+//synthesis translate_off
+module tb ;
+       parameter tCYC=2 ;
+       parameter tPD=(tCYC/10) ;
+
+       integer i ;
+
+       reg  p_reset, m_clock ;
+       reg  [13:0] iRadrs ;
+       wire [15:0] oRdata ;
+       reg             fiRd_req ;
+       wire            foRd_ack ;
+       
+       reg  [7:0]      iWdata ;
+       reg  [13:0] iWadrs ;
+       reg             fiWr_req ;
+
+       exp_ctrl uut(
+               .p_reset(p_reset),
+               .m_clock(m_clock),
+               .iRadrs(iRadrs),
+               .oRdata(oRdata),
+               .fiRd_req(fiRd_req),
+               .foRd_ack(foRd_ack),
+               .iWdata(iWdata),
+               .iWadrs(iWadrs),
+               .fiWr_req(fiWr_req)
+       ) ;
+
+       initial forever #(tCYC/2) m_clock = ~m_clock ;
+
+       initial begin
+               #(tPD)
+                       p_reset = 1 ;
+                       m_clock = 0 ;
+                       // Initialize
+                       iRadrs   <= 14'd0 ;
+                       fiRd_req <= 0 ;
+                       iWdata   <= 8'd0 ;
+                       iWadrs   <= 14'd0 ;
+                       fiWr_req <= 0 ;
+               #(tCYC)
+                       p_reset = 0 ;
+               #(tCYC*5) ;
+                       for(i=0; i<1000; i=i+1) begin
+                               fiWr_req <= 1 ;
+                               iWdata <= i[7:0] ;
+                               iWadrs <= i[13:0] ;
+                       #(tCYC) ;
+                               fiWr_req <= 0 ;
+                       #(tCYC) ;
+                       end
+               #(tCYC*5) ;
+                       for(i=0; i<100; i=i+1) begin
+                               fiRd_req <= 1 ;
+                               iRadrs <= i[13:0] ;
+                       #(tCYC) ;
+                               fiRd_req <= 0 ;
+                       #(tCYC*2) ;
+                       end
+       end
+
+endmodule
+
+//synthesis translate_on