scroll reg bug fixed, but this time it turns out to have vram bank defect...

diff --git a/de1_nes/de1_nes.vhd b/de1_nes/de1_nes.vhd
index d2b5b6c..e1ab68e 100644 (file)
--- a/de1_nes/de1_nes.vhd
+++ b/de1_nes/de1_nes.vhd
@@ -369,16 +369,16 @@ begin
 --    dbg_status <= dbg_nes_y(7 downto 0);
 
 
-    dbg_ppu_scrl_x(0) <= ale;
-    dbg_ppu_scrl_x(1) <= rd_n;
-    dbg_ppu_scrl_x(2) <= wr_n;
-    dbg_ppu_scrl_x(3) <= nt0_ce_n;
-    dbg_ppu_scrl_x(4) <= vga_clk;
-    dbg_ppu_scrl_x(5) <= rom_ce_n;
-    dbg_ppu_scrl_x(6) <= ram_ce_n;
-    dbg_ppu_scrl_x(7) <= addr(15);
-    dbg_ppu_scrl_y(2 downto 0) <= dbg_p_oam_ce_rn_wn(2 downto 0);
-    dbg_ppu_scrl_y(5 downto 3) <= dbg_plt_ce_rn_wn(2 downto 0);
+--    dbg_ppu_scrl_x(0) <= ale;
+--    dbg_ppu_scrl_x(1) <= rd_n;
+--    dbg_ppu_scrl_x(2) <= wr_n;
+--    dbg_ppu_scrl_x(3) <= nt0_ce_n;
+--    dbg_ppu_scrl_x(4) <= vga_clk;
+--    dbg_ppu_scrl_x(5) <= rom_ce_n;
+--    dbg_ppu_scrl_x(6) <= ram_ce_n;
+--    dbg_ppu_scrl_x(7) <= addr(15);
+--    dbg_ppu_scrl_y(2 downto 0) <= dbg_p_oam_ce_rn_wn(2 downto 0);
+--    dbg_ppu_scrl_y(5 downto 3) <= dbg_plt_ce_rn_wn(2 downto 0);
     dbg_disp_ptn_l (7 downto 0) <= dbg_p_oam_addr;
     dbg_disp_ptn_l (15 downto 8) <= dbg_p_oam_data;
 
@@ -403,7 +403,7 @@ begin
         dbg_ppu_ce_n                                        ,
         dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status          ,
         dbg_ppu_addr                                        ,
-        dbg_ppu_data, dbg_ppu_scrl_x_dummy, dbg_ppu_scrl_y_dummy        ,
+        dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y        ,
 
         dbg_ppu_clk                      ,
         dbg_vga_clk                      ,

diff --git a/de1_nes/dummy-mos6502.vhd b/de1_nes/dummy-mos6502.vhd
index 934cc66..b35fd17 100644 (file)
--- a/de1_nes/dummy-mos6502.vhd
+++ b/de1_nes/dummy-mos6502.vhd
@@ -469,7 +469,7 @@ end;
                         --step4 = scroll test.\r
                         if (scl_step_cnt = 0) then\r
                             --x scroll pos=40\r
-                            io_out(16#2005#, 140);\r
+                            io_out(16#2005#, 40);\r
                         elsif (scl_step_cnt = 1 * cpu_io_multi) then\r
                             --y scroll pos=3\r
                             io_out(16#2005#, 3);\r

diff --git a/de1_nes/ppu/ppu.vhd b/de1_nes/ppu/ppu.vhd
index 5ed8d65..279d1a8 100644 (file)
--- a/de1_nes/ppu/ppu.vhd
+++ b/de1_nes/ppu/ppu.vhd
@@ -313,21 +313,19 @@ begin
             ppu_mask_we_n    <= '1';
             oam_addr_we_n    <= '1';
             oam_data_we_n    <= '1';
-            ppu_scroll_x_we_n    <= '1';
-            ppu_scroll_y_we_n    <= '1';
             ppu_scroll_cnt_ce_n  <= '1';
             read_status <= '0';
             read_data_n <= '1';
         elsif (rst_n = '1' and ce_n = '0') then
 
             --register set.
-            if(cpu_addr = PPUCTRL) then
+            if(cpu_addr = PPUCTRL and r_nw = '0') then
                 ppu_ctrl_we_n <= '0';
             else
                 ppu_ctrl_we_n <= '1';
             end if;
 
-            if(cpu_addr = PPUMASK) then
+            if(cpu_addr = PPUMASK and r_nw = '0') then
                 ppu_mask_we_n <= '0';
             else
                 ppu_mask_we_n <= '1';
@@ -340,30 +338,21 @@ begin
                 read_status <= '0';
             end if;
 
-            if(cpu_addr = OAMADDR) then
+            if(cpu_addr = OAMADDR and r_nw = '0') then
                 oam_addr_we_n <= '0';
             else
                 oam_addr_we_n <= '1';
             end if;
 
-            if(cpu_addr = OAMDATA) then
+            if(cpu_addr = OAMDATA and r_nw = '0') then
                 oam_data_we_n <= '0';
             else
                 oam_data_we_n <= '1';
             end if;
 
-            if(cpu_addr = PPUSCROLL) then
+            if(cpu_addr = PPUSCROLL and r_nw = '0') then
                 ppu_scroll_cnt_ce_n <= '0';
-                if (ppu_scroll_cnt(0) = '0') then
-                    ppu_scroll_x_we_n <= '0';
-                    ppu_scroll_y_we_n <= '1';
-                else
-                    ppu_scroll_y_we_n <= '0';
-                    ppu_scroll_x_we_n <= '1';
-                end if;
             else
-                ppu_scroll_x_we_n <= '1';
-                ppu_scroll_y_we_n <= '1';
                 ppu_scroll_cnt_ce_n <= '1';
             end if;
 
@@ -377,8 +366,6 @@ begin
             ppu_mask_we_n    <= '1';
             oam_addr_we_n    <= '1';
             oam_data_we_n    <= '1';
-            ppu_scroll_x_we_n    <= '1';
-            ppu_scroll_y_we_n    <= '1';
             ppu_scroll_cnt_ce_n  <= '1';
             read_status <= '0';
             read_data_n <= '1';
@@ -388,6 +375,28 @@ begin
 
     ppu_clk_cnt_res_n <= not ce_n;
 
+    --scroll reg...
+    scl_reg_p : process (rst_n, ppu_clk)
+    begin
+        if (rst_n = '0') then
+            ppu_scroll_x_we_n <= '1';
+            ppu_scroll_y_we_n <= '1';
+        elsif (rising_edge(ppu_clk)) then
+            if (ppu_scroll_cnt_ce_n = '0' and ppu_clk_cnt = "01" and r_nw = '0') then
+                if (ppu_scroll_cnt(0) = '1') then
+                    ppu_scroll_x_we_n <= '0';
+                    ppu_scroll_y_we_n <= '1';
+                else
+                    ppu_scroll_y_we_n <= '0';
+                    ppu_scroll_x_we_n <= '1';
+                end if;
+            else
+                ppu_scroll_x_we_n <= '1';
+                ppu_scroll_y_we_n <= '1';
+            end if;
+        end if;
+    end process;
+
     --cpu nmi generation...
     clk_nmi_p : process (rst_n, ppu_clk)
     begin

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
index d6ee878..fcced4e 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
@@ -60,6 +60,8 @@ add wave -label ppu_mask  -radix hex sim:/testbench_motones_sim/sim_board/dbg_pp
 add wave -label ppu_status   -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status\r
 add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_addr\r
 add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_data\r
+add wave -label ppu_scrl_x -radix decimal -unsigned  sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x\r
+add wave -label ppu_scrl_y -radix decimal -unsigned  sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y\r
 \r
 \r
 #add wave -divider vga_pos\r
@@ -81,9 +83,9 @@ add wave  -radix hex -label vram_ad sim:/testbench_motones_sim/sim_board/dbg_vra
 #add wave -label plt_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(5)\r
 #add wave -label plt_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(4)\r
 #add wave -label plt_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(3)\r
-add wave -label oam_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(2)\r
-add wave -label oam_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(1)\r
-add wave -label oam_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(0)\r
+#add wave -label oam_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(2)\r
+#add wave -label oam_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(1)\r
+#add wave -label oam_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(0)\r
 #add wave  -radix hex -label plt_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(12 downto 8)}\r
 #add wave  -radix hex -label plt_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(7 downto 0)}\r
 \r
@@ -108,7 +110,7 @@ wave zoom full
 \r
 #wave zoom range 3339700 ps 5138320 ps\r
 \r
-run 138 us\r
+#run 138 us\r
 \r
 ##wave addcursor 907923400 ps\r
 \r

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
index 3481138..1adaac4 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
@@ -18,9 +18,9 @@ vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/mem/prg_rom.vhd}
 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/mem/chr_rom.vhd}\r
 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/mem/ram.vhd}\r
 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/apu/apu.vhd}\r
-#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/ppu_registers.vhd}\r
-#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/ppu.vhd}\r
-#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/vga_ppu.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/ppu_registers.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/ppu.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/vga_ppu.vhd}\r
 #vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/cpu_registers.vhd}\r
 #vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/alu.vhd}\r
 #vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/decoder.vhd}\r
@@ -54,34 +54,38 @@ add wave -label d_io -radix hex sim:/testbench_motones_sim/sim_board/d_io
 \r
 ##add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_reg\r
 \r
-#add wave -divider ppu\r
-#\r
-#add wave  -label cpu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_addr\r
-#add wave  -label cpu_d -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_d\r
-#\r
-#add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
-#add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
-#\r
-#add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
-#\r
-#add wave -label ppu_ctl -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_ctrl\r
-#add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_mask\r
-#add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_status\r
-#\r
-#\r
-##add wave -label ppu_addr_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_cnt\r
-##add wave -label ppu_addr_we_n -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_we_n\r
-##add wave -label ppu_addr_in -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_in\r
-##add wave -label ppu_addr_inc1 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc1\r
-##add wave -label ppu_addr_inc32 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc32\r
-#\r
-#add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr\r
-#add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_data\r
-##add wave -label ppu_scr_x -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scrl_x\r
-##add wave -label ppu_scr_y -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scrl_y\r
-#\r
-####add wave sim:/testbench_motones_sim/sim_board/cpu_inst/*\r
-#\r
+add wave -divider ppu\r
+add wave  -label cpu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_addr\r
+add wave  -label cpu_d -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_d\r
+add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
+add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
+add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
+add wave -label ppu_ctl -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_ctrl\r
+add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_mask\r
+add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_status\r
+#add wave -label ppu_addr_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_cnt\r
+#add wave -label ppu_addr_we_n -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_we_n\r
+#add wave -label ppu_addr_in -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_in\r
+#add wave -label ppu_addr_inc1 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc1\r
+#add wave -label ppu_addr_inc32 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc32\r
+add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr\r
+add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_data\r
+\r
+\r
+add wave -divider ppu_scrl\r
+add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
+add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
+add wave -label ppu_scroll_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_cnt\r
+\r
+add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
+\r
+add wave -label ppu_scroll_cnt_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_cnt_ce_n\r
+add wave -label ppu_scroll_x_we_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x_we_n\r
+add wave -label ppu_scroll_y_we_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y_we_n\r
+add wave -label ppu_scr_x -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x\r
+add wave -label ppu_scr_y -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y\r
+\r
+\r
 #add wave -divider render\r
 #\r
 ##add wave -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/pos_x \\r
@@ -96,20 +100,16 @@ add wave -label d_io -radix hex sim:/testbench_motones_sim/sim_board/d_io
 \r
 \r
 \r
-add wave -divider apu\r
-\r
-add wave  -label cpu_addr sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n\r
-add wave  -label dma_next_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_next_status\r
-add wave  -label dma_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_status\r
-add wave  -label dma_cnt_ce sim:/testbench_motones_sim/sim_board/apu_inst/dma_cnt_ce\r
-add wave  -label rdy sim:/testbench_motones_sim/sim_board/apu_inst/rdy\r
-\r
-add wave  -label dma_write_we_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_write_we_n\r
-add wave  -label dma_addr -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_addr\r
-\r
-\r
-add wave  -label dma_start_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n\r
-add wave  -label dma_end_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_end_n\r
+#add wave -divider apu\r
+#add wave  -label cpu_addr sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n\r
+#add wave  -label dma_next_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_next_status\r
+#add wave  -label dma_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_status\r
+#add wave  -label dma_cnt_ce sim:/testbench_motones_sim/sim_board/apu_inst/dma_cnt_ce\r
+#add wave  -label rdy sim:/testbench_motones_sim/sim_board/apu_inst/rdy\r
+#add wave  -label dma_write_we_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_write_we_n\r
+#add wave  -label dma_addr -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_addr\r
+#add wave  -label dma_start_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n\r
+#add wave  -label dma_end_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_end_n\r
 \r
 \r
 \r
@@ -119,5 +119,5 @@ view signals
 run 8 us\r
 wave zoom full\r
 \r
-run 430 us\r
+#run 430 us\r
 \r