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b43: HT-PHY: implement PA override
authorRafał Miłecki <zajec5@gmail.com>
Sat, 9 Mar 2013 12:49:01 +0000 (13:49 +0100)
committerJohn W. Linville <linville@tuxdriver.com>
Wed, 13 Mar 2013 18:27:49 +0000 (14:27 -0400)
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/b43/phy_ht.c
drivers/net/wireless/b43/phy_ht.h

index 23a46c6..1998dca 100644 (file)
@@ -178,6 +178,26 @@ static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
        b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
 }
 
+static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable)
+{
+       struct b43_phy_ht *htphy = dev->phy.ht;
+       static const u16 regs[3] = { B43_PHY_HT_RF_CTL_INT_C1,
+                                    B43_PHY_HT_RF_CTL_INT_C2,
+                                    B43_PHY_HT_RF_CTL_INT_C3 };
+       int i;
+
+       if (enable) {
+               for (i = 0; i < 3; i++)
+                       b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]);
+       } else {
+               for (i = 0; i < 3; i++)
+                       htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]);
+               /* TODO: Does 5GHz band use different value (not 0x0400)? */
+               for (i = 0; i < 3; i++)
+                       b43_phy_write(dev, regs[i], 0x0400);
+       }
+}
+
 /**************************************************
  * Various PHY ops
  **************************************************/
@@ -554,8 +574,10 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
 
        b43_mac_phy_clock_set(dev, true);
 
+       b43_phy_ht_pa_override(dev, false);
        b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
        b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
+       b43_phy_ht_pa_override(dev, true);
 
        /* TODO: Should we restore it? Or store it in global PHY info? */
        b43_phy_ht_classifier(dev, 0, 0);
index 52603af..684807c 100644 (file)
 
 #define B43_PHY_HT_RF_CTL1                     B43_PHY_EXTG(0x010)
 
+#define B43_PHY_HT_RF_CTL_INT_C1               B43_PHY_EXTG(0x04c)
+#define B43_PHY_HT_RF_CTL_INT_C2               B43_PHY_EXTG(0x06c)
+#define B43_PHY_HT_RF_CTL_INT_C3               B43_PHY_EXTG(0x08c)
+
 #define B43_PHY_HT_AFE_C1_OVER                 B43_PHY_EXTG(0x110)
 #define B43_PHY_HT_AFE_C1                      B43_PHY_EXTG(0x111)
 #define B43_PHY_HT_AFE_C2_OVER                 B43_PHY_EXTG(0x114)
@@ -62,6 +66,7 @@ struct b43_phy_ht_channeltab_e_phy {
 
 
 struct b43_phy_ht {
+       u16 rf_ctl_int_save[3];
 };