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arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling
authorGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 19 Aug 2020 13:43:44 +0000 (15:43 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 10 Nov 2020 08:29:47 +0000 (09:29 +0100)
Some EtherAVB variants support internal clock delay configuration, which
can add larger delays than the delays that are typically supported by
the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
properties).

Historically, the EtherAVB driver configured these delays based on the
"rgmii-*id" PHY mode.  This was wrong, as these are meant solely for the
PHY, not for the MAC.  Hence properties were introduced for explicit
configuration of these delays.

Convert the RZ/G2 DTS files from the old to the new scheme:
  - Add default "rx-internal-delay-ps" and "tx-internal-delay-ps"
    properties to the SoC .dtsi files, to be overridden by board files
    where needed,
  - Convert board files from "rgmii-*id" PHY modes to "rgmii", adding
    the appropriate "rx-internal-delay-ps" and/or "tx-internal-delay-ps"
    overrides.

Notes:
  - RZ/G2E does not support TX internal delay handling.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200819134344.27813-8-geert+renesas@glider.be
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
arch/arm64/boot/dts/renesas/r8a774e1.dtsi

index 97272f5..8ac167a 100644 (file)
@@ -55,7 +55,8 @@
        pinctrl-0 = <&avb_pins>;
        pinctrl-names = "default";
        phy-handle = <&phy0>;
-       phy-mode = "rgmii-id";
+       rx-internal-delay-ps = <1800>;
+       tx-internal-delay-ps = <2000>;
        status = "okay";
 
        phy0: ethernet-phy@0 {
index b9e46ae..202c4fc 100644 (file)
@@ -19,7 +19,7 @@
        pinctrl-0 = <&avb_pins>;
        pinctrl-names = "default";
        phy-handle = <&phy0>;
-       phy-mode = "rgmii-txid";
+       tx-internal-delay-ps = <2000>;
        status = "okay";
 
        phy0: ethernet-phy@0 {
index c15f1c5..d37ec42 100644 (file)
                        power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
                        resets = <&cpg 812>;
                        phy-mode = "rgmii";
+                       rx-internal-delay-ps = <0>;
+                       tx-internal-delay-ps = <0>;
                        iommus = <&ipmmu_ds0 16>;
                        #address-cells = <1>;
                        #size-cells = <0>;
index 39a1a26..8352391 100644 (file)
                        power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
                        resets = <&cpg 812>;
                        phy-mode = "rgmii";
+                       rx-internal-delay-ps = <0>;
+                       tx-internal-delay-ps = <0>;
                        iommus = <&ipmmu_ds0 16>;
                        #address-cells = <1>;
                        #size-cells = <0>;
index f27d9b2..e0e5434 100644 (file)
                        power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
                        resets = <&cpg 812>;
                        phy-mode = "rgmii";
+                       rx-internal-delay-ps = <0>;
                        iommus = <&ipmmu_ds0 16>;
                        #address-cells = <1>;
                        #size-cells = <0>;
index 9cbf963..31ae353 100644 (file)
                        power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
                        resets = <&cpg 812>;
                        phy-mode = "rgmii";
+                       rx-internal-delay-ps = <0>;
+                       tx-internal-delay-ps = <0>;
                        iommus = <&ipmmu_ds0 16>;
                        #address-cells = <1>;
                        #size-cells = <0>;