dts: bindings: Document device tree binding for CATU

Document CATU device-tree bindings. CATU augments the TMC-ETR
by providing an improved Scatter Gather mechanism for streaming
trace data to non-contiguous system RAM pages.

Cc: devicetree@vger.kernel.org
Cc: frowand.list@gmail.com
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 9aa30a1..5d1ad09 100644 (file)
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -39,6 +39,8 @@ its hardware characteristcs.
 
                - System Trace Macrocell:
                        "arm,coresight-stm", "arm,primecell"; [1]
+               - Coresight Address Translation Unit (CATU)
+                       "arm,coresight-catu", "arm,primecell";
 
        * reg: physical base address and length of the register
          set(s) of the component.
@@ -90,6 +92,10 @@ its hardware characteristcs.
        * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
          use the SG mode on this system.
 
+* Optional property for CATU :
+       * interrupts : Exactly one SPI may be listed for reporting the address
+         error
+
 Example:
 
 1. Sinks
@@ -121,6 +127,35 @@ Example:
                };
        };
 
+       etr@20070000 {
+               compatible = "arm,coresight-tmc", "arm,primecell";
+               reg = <0 0x20070000 0 0x1000>;
+
+               clocks = <&oscclk6a>;
+               clock-names = "apb_pclk";
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       /* input port */
+                       port@0 {
+                               reg =  <0>;
+                               etr_in_port: endpoint {
+                                       slave-mode;
+                                       remote-endpoint = <&replicator2_out_port0>;
+                               };
+                       };
+
+                       /* CATU link represented by output port */
+                       port@1 {
+                               reg = <1>;
+                               etr_out_port: endpoint {
+                                       remote-endpoint = <&catu_in_port>;
+                               };
+                       };
+               };
+       };
+
 2. Links
        replicator {
                /* non-configurable replicators don't show up on the
@@ -250,5 +285,23 @@ Example:
                };
        };
 
+5. CATU
+
+       catu@207e0000 {
+               compatible = "arm,coresight-catu", "arm,primecell";
+               reg = <0 0x207e0000 0 0x1000>;
+
+               clocks = <&oscclk6a>;
+               clock-names = "apb_pclk";
+
+               interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+               port {
+                       catu_in_port: endpoint {
+                               slave-mode;
+                               remote-endpoint = <&etr_out_port>;
+                       };
+               };
+       };
+
 [1]. There is currently two version of STM: STM32 and STM500.  Both
 have the same HW interface and as such don't need an explicit binding name.