Add support for MIPS R1[02]000 performance counter opcodes.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 2e3c63f..13c3b4e 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2001-08-16  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+       * gas/mips/mips.exp: Added performance counter test.
+       * gas/mips/perfcount.s: New File. Test of performance counter opcodes.
+       * gas/mips/perfcount.d: Likewise.
+
 2001-08-12  Nick Clifton  <nickc@cambridge.redhat.com>
 
        * gas/sparc/unalign.s: Extend test to check .uaword with multiple

diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 678b470..0263008 100644 (file)
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -111,6 +111,7 @@ if { [istarget mips*-*-*] } then {
     run_dump_test "mips4010"
     run_dump_test "mips4650"
     run_dump_test "mips4100"
+    run_dump_test "perfcount"
     # Linux uses ELF stabs, which doesn't support line number.
     setup_xfail "mips*-*-*linux*"
     run_dump_test "lineno"

diff --git a/gas/testsuite/gas/mips/perfcount.d b/gas/testsuite/gas/mips/perfcount.d
new file mode 100644 (file)
index 0000000..1f0203a
--- /dev/null
+++ b/gas/testsuite/gas/mips/perfcount.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses -mmips:10000
+#name: MIPS R1[20]000 performance counters
+#as: -mips4 -march=r10000
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> mtps    a0,0
+0+0004 <[^>]*> mfps    a0,1
+0+0008 <[^>]*> mtpc    a0,1
+0+000c <[^>]*> mfpc    a0,0

diff --git a/gas/testsuite/gas/mips/perfcount.s b/gas/testsuite/gas/mips/perfcount.s
new file mode 100644 (file)
index 0000000..9e0f7b2
--- /dev/null
+++ b/gas/testsuite/gas/mips/perfcount.s
@@ -0,0 +1,7 @@
+# source file to test assembly of R1[20]000 performance counter instructions.
+
+foo:
+       mtps    $4, 0
+       mfps    $4, 1
+       mtpc    $4, 1
+       mfpc    $4, 0

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index b95cf1e..981de9e 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2001-08-16  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+       * mips.h (INSN_10000): Define.
+       (OPCODE_IS_MEMBER): Check for INSN_10000.
+
 2001-08-10  Alan Modra  <amodra@one.net.au>
 
        * ppc.h: Revert 2001-08-08.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 23e6028..349d266 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -326,6 +326,8 @@ struct mips_opcode
 #define INSN_4100                 0x00040000
 /* Toshiba R3900 instruction.  */
 #define INSN_3900                 0x00080000
+/* MIPS R10000 instruction.  */
+#define INSN_10000                0x00100000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -375,7 +377,9 @@ struct mips_opcode
      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)    \
      || ((cpu == CPU_VR4100 || cpu == CPU_R4111)                       \
         && ((insn)->membership & INSN_4100) != 0)                      \
-     || (cpu == CPU_R3900  && ((insn)->membership & INSN_3900) != 0))
+     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)    \
+     || ((cpu == CPU_R10000 || cpu == CPU_R12000)                      \
+        && ((insn)->membership & INSN_10000) != 0))
 
 /* This is a list of macro expanded instructions.
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 50fb25b..add1029 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2001-08-16  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+       * mips-opc.c (M1): Define. Reformatted Code.
+       (mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps,
+       mtps, mtps. Typo.
+
 2001-08-16  Jonathan Larmour  <jlarmour@redhat.com>
 
        * mips-opc.c: R3900s can support all branch likely INSN_MACROs where

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index b12518a..5c2c792 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -86,15 +86,16 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define L1     INSN_4010
 #define V1      INSN_4100
 #define T3      INSN_3900
+#define M1     INSN_10000
 
 #define G1      (T3             \
                  )
 
-#define G2      (T3                   \
+#define G2      (T3             \
                  )
 
-#define G3 (I4             \
-            )
+#define G3      (I4             \
+                 )
 
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
@@ -557,6 +558,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      G1        },
 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1        },
 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          V1 },
+{"mfpc",    "t,P",     0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0,         M1      },
+{"mfps",    "t,P",     0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0,         M1      },
 {"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         I1      },
 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        I32     },
 {"mfc1",    "t,S",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I1      },
@@ -594,6 +597,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     I32     },
 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,     L1      },
 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     I32     },
+{"mtpc",    "t,P",     0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         M1      },
+{"mtps",    "t,P",     0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         M1      },
 {"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   I1      },
 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I32     },
 {"mtc1",    "t,S",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I1      },
@@ -836,7 +841,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
-   disasembler recognizes more specific versions first.  */
+   disassembler recognizes more specific versions first.  */
 {"c0",      "C",       0x42000000, 0xfe000000, 0,                      I1      },
 {"c1",      "C",       0x46000000, 0xfe000000, 0,                      I1      },
 {"c2",      "C",       0x4a000000, 0xfe000000, 0,                      I1      },