return offsetof(CPUPPCState, vsr[i].u64[0]);
}
+static inline int acc_full_offset(int i)
+{
+ return vsr_full_offset(i * 4);
+}
+
static inline int fpr_offset(int i)
{
return vsr64_offset(i, true);
&X_vrt_frbp vrt frbp
@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
+&X_a ra
+@X_a ...... ra:3 .. ..... ..... .......... . &X_a
+
%xx_xt 0:1 21:5
%xx_xb 1:1 11:5
%xx_xa 2:1 16:5
&XL_s s:uint8_t
@XL_s ......-------------- s:1 .......... - &XL_s
RFEBB 010011-------------- . 0010010010 - @XL_s
+
+## Accumulator Instructions
+
+XXMFACC 011111 ... -- 00000 ----- 0010110001 - @X_a
+XXMTACC 011111 ... -- 00001 ----- 0010110001 - @X_a
+XXSETACCZ 011111 ... -- 00011 ----- 0010110001 - @X_a
return true;
}
+ /*
+ * The PowerISA 3.1 mentions that for the current version of the
+ * architecture, "the hardware implementation provides the effect of
+ * ACC[i] and VSRs 4*i to 4*i + 3 logically containing the same data"
+ * and "The Accumulators introduce no new logical state at this time"
+ * (page 501). For now it seems unnecessary to create new structures,
+ * so ACC[i] is the same as VSRs 4*i to 4*i+3 and therefore
+ * move to and from accumulators are no-ops.
+ */
+static bool trans_XXMFACC(DisasContext *ctx, arg_X_a *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+ return true;
+}
+
+static bool trans_XXMTACC(DisasContext *ctx, arg_X_a *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+ return true;
+}
+
+static bool trans_XXSETACCZ(DisasContext *ctx, arg_X_a *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+ tcg_gen_gvec_dup_imm(MO_64, acc_full_offset(a->ra), 64, 64, 0);
+ return true;
+}
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM