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[X86] Update folding table generator to properly detect RMW arithmetic instructions.
author
Craig Topper
<craig.topper@intel.com>
Tue, 12 Jun 2018 07:32:15 +0000
(07:32 +0000)
committer
Craig Topper
<craig.topper@intel.com>
Tue, 12 Jun 2018 07:32:15 +0000
(07:32 +0000)
The RMW instructions are detected by reading the SchedRW data, but the RMW instructions have had their SchedRW changed in recent months. This broke the expectation.
We probably should fix this to use the mayLoad/mayStore flags if possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334478
91177308
-0d34-0410-b5e6-
96231b3b80d8
utils/TableGen/X86FoldTablesEmitter.cpp
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diff --git
a/utils/TableGen/X86FoldTablesEmitter.cpp
b/utils/TableGen/X86FoldTablesEmitter.cpp
index
1ebe9f9
..
6ef339b
100644
(file)
--- a/
utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/
utils/TableGen/X86FoldTablesEmitter.cpp
@@
-517,8
+517,10
@@
void X86FoldTablesEmitter::updateTables(const CodeGenInstruction *RegInstr,
// Instructions which have the WriteRMW value (Read-Modify-Write) should be
// added to Table2Addr.
- if (hasDefInList(MemRec, "SchedRW", "WriteRMW") && MemOutSize != RegOutSize &&
- MemInSize == RegInSize) {
+ if ((hasDefInList(MemRec, "SchedRW", "WriteRMW") ||
+ hasDefInList(MemRec, "SchedRW", "WriteADCRMW") ||
+ hasDefInList(MemRec, "SchedRW", "WriteALURMW")) &&
+ MemOutSize != RegOutSize && MemInSize == RegInSize) {
addEntryWithFlags(Table2Addr, RegInstr, MemInstr, S, 0);
return;
}