+2008-10-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (processor_type): Moved to tc-i386.h.
+ (cpu_arch_tune): Make it global.
+ (cpu_arch_isa): Likewise.
+ (cpu_arch_isa_flags): Likewise.
+ (i386_align_code): Check fragP->tc_frag_data.isa,
+ fragP->tc_frag_data.isa_flags and cpu_arch_tune instead of
+ cpu_arch_isa, cpu_arch_isa_flags and cpu_arch_tune,
+ respectively.
+
+ * config/tc-i386.h (processor_type): Moved from tc-i386.c.
+ (cpu_arch_tune): New.
+ (cpu_arch_isa): Likewise.
+ (cpu_arch_isa_flags): Likewise.
+ (i386_tc_frag_data): Likewise.
+ (TC_FRAG_TYPE): Likewise.
+ (TC_FRAG_INIT): Likewise.
+
2008-10-09 Bob Wilson <bob.wilson@acm.org>
* doc/as.texinfo (Pseudo Ops): Swap order of Comm and CFI menu entries.
}
sib_byte;
-enum processor_type
-{
- PROCESSOR_UNKNOWN,
- PROCESSOR_I386,
- PROCESSOR_I486,
- PROCESSOR_PENTIUM,
- PROCESSOR_PENTIUMPRO,
- PROCESSOR_PENTIUM4,
- PROCESSOR_NOCONA,
- PROCESSOR_CORE,
- PROCESSOR_CORE2,
- PROCESSOR_K6,
- PROCESSOR_ATHLON,
- PROCESSOR_K8,
- PROCESSOR_GENERIC32,
- PROCESSOR_GENERIC64,
- PROCESSOR_AMDFAM10
-};
-
/* x86 arch names, types and features */
typedef struct
{
static int cpu_arch_tune_set = 0;
/* Cpu we are generating instructions for. */
-static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
+enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
/* CPU feature flags of cpu we are generating instructions for. */
static i386_cpu_flags cpu_arch_tune_flags;
/* CPU instruction set architecture used. */
-static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
+enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
/* CPU feature flags of instruction set architecture used. */
-static i386_cpu_flags cpu_arch_isa_flags;
+i386_cpu_flags cpu_arch_isa_flags;
/* If set, conditional jumps are not automatically promoted to handle
larger than a byte offset. */
{
const char *const *patt = NULL;
- if (cpu_arch_isa == PROCESSOR_UNKNOWN)
+ if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
{
/* PROCESSOR_UNKNOWN means that all ISAs may be used. */
switch (cpu_arch_tune)
case PROCESSOR_UNKNOWN:
/* We use cpu_arch_isa_flags to check if we SHOULD
optimize for Cpu686. */
- if (cpu_arch_isa_flags.bitfield.cpui686)
+ if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
patt = alt_long_patt;
else
patt = f32_patt;
}
else
{
- switch (cpu_arch_tune)
+ switch (fragP->tc_frag_data.tune)
{
case PROCESSOR_UNKNOWN:
/* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
case PROCESSOR_GENERIC32:
/* We use cpu_arch_isa_flags to check if we CAN optimize
for Cpu686. */
- if (cpu_arch_isa_flags.bitfield.cpui686)
+ if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
patt = alt_short_patt;
else
patt = f32_patt;
case PROCESSOR_NOCONA:
case PROCESSOR_CORE:
case PROCESSOR_CORE2:
- if (cpu_arch_isa_flags.bitfield.cpui686)
+ if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
patt = alt_long_patt;
else
patt = f32_patt;
#define md_number_to_chars number_to_chars_littleendian
+enum processor_type
+{
+ PROCESSOR_UNKNOWN,
+ PROCESSOR_I386,
+ PROCESSOR_I486,
+ PROCESSOR_PENTIUM,
+ PROCESSOR_PENTIUMPRO,
+ PROCESSOR_PENTIUM4,
+ PROCESSOR_NOCONA,
+ PROCESSOR_CORE,
+ PROCESSOR_CORE2,
+ PROCESSOR_K6,
+ PROCESSOR_ATHLON,
+ PROCESSOR_K8,
+ PROCESSOR_GENERIC32,
+ PROCESSOR_GENERIC64,
+ PROCESSOR_AMDFAM10
+};
+
+extern enum processor_type cpu_arch_tune;
+extern enum processor_type cpu_arch_isa;
+extern i386_cpu_flags cpu_arch_isa_flags;
+
+struct i386_tc_frag_data
+{
+ enum processor_type isa;
+ i386_cpu_flags isa_flags;
+ enum processor_type tune;
+};
+
+/* We need to emit the right NOP pattern in .align frags. This is
+ done after the text-to-bits assembly pass, so we need to mark it with
+ the isa/tune settings at the time the .align was assembled. */
+#define TC_FRAG_TYPE struct i386_tc_frag_data
+
+#define TC_FRAG_INIT(FRAGP) \
+ do \
+ { \
+ (FRAGP)->tc_frag_data.isa = cpu_arch_isa; \
+ (FRAGP)->tc_frag_data.isa_flags = cpu_arch_isa_flags; \
+ (FRAGP)->tc_frag_data.tune = cpu_arch_tune; \
+ } \
+ while (0)
+
#ifdef SCO_ELF
#define tc_init_after_args() sco_id ()
extern void sco_id (void);
+2008-10-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run nops-5, nops-5-i686, x86-64-nops-5 and
+ x86-64-nops-5-k8.
+
+ * gas/i386/nops-5.d: New.
+ * gas/i386/nops-5.s: Likewise.
+ * gas/i386/nops-5-i686.d: Likewise.
+ * gas/i386/x86-64-nops-5.d: Likewise.
+ * gas/i386/x86-64-nops-5-k8.d: Likewise.
+
2008-10-06 Tom Tromey <tromey@redhat.com>
* gas/cfi/cfi-alpha-1.d, gas/cfi/cfi-alpha-3.d,
run_dump_test "nops-4"
run_dump_test "nops-4-i386"
run_dump_test "nops-4-i686"
+ run_dump_test "nops-5"
+ run_dump_test "nops-5-i686"
run_dump_test "addr16"
run_dump_test "addr32"
run_dump_test "sse4_1"
run_dump_test "x86-64-nops-4"
run_dump_test "x86-64-nops-4-core2"
run_dump_test "x86-64-nops-4-k8"
+ run_dump_test "x86-64-nops-5"
+ run_dump_test "x86-64-nops-5-k8"
run_dump_test "x86-64-sse4_1"
run_dump_test "x86-64-sse4_1-intel"
run_dump_test "x86-64-sse4_2"
--- /dev/null
+#as: -march=i686
+#source: nops-5.s
+#objdump: -drw
+#name: i386 -march=i686 nops 5
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <i386>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%esi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi,%eiz,1\),%edi
+
+0+10 <i486>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%esi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi,%eiz,1\),%edi
+
+0+20 <i586>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%esi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi,%eiz,1\),%edi
+
+0+30 <i686>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\)
+
+0+40 <pentium4>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\)
+
+0+50 <nocona>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\)
+
+0+60 <core>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\)
+
+0+70 <core2>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\)
+
+0+80 <k6>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%esi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi,%eiz,1\),%edi
+
+0+90 <athlon>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\)
+[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\)
+
+0+a0 <k8>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\)
+[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\)
+
+0+b0 <generic32>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%esi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi,%eiz,1\),%edi
+
+0+c0 <generic64>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\)
+
+0+d0 <amdfam10>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\)
+[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\)
+#pass
--- /dev/null
+#objdump: -drw
+#name: i386 nops 5
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <i386>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%esi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi,%eiz,1\),%edi
+
+0+10 <i486>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%esi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi,%eiz,1\),%edi
+
+0+20 <i586>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%esi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi,%eiz,1\),%edi
+
+0+30 <i686>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\)
+
+0+40 <pentium4>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\)
+
+0+50 <nocona>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\)
+
+0+60 <core>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\)
+
+0+70 <core2>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\)
+
+0+80 <k6>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%esi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi,%eiz,1\),%edi
+
+0+90 <athlon>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\)
+[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\)
+
+0+a0 <k8>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\)
+[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\)
+
+0+b0 <generic32>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%esi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi,%eiz,1\),%edi
+
+0+c0 <generic64>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\)
+
+0+d0 <amdfam10>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\)
+[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\)
+#pass
--- /dev/null
+ .text
+ .arch i386
+i386:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch i486
+i486:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch i586
+i586:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch i686
+i686:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch pentium4
+pentium4:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch nocona
+nocona:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch core
+core:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch core2
+core2:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch k6
+k6:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch athlon
+athlon:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch k8
+k8:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch generic32
+generic32:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch generic64
+generic64:
+ movsbl %al,%esi
+ .p2align 4
+
+ .arch amdfam10
+amdfam10:
+ movsbl %al,%esi
+ .p2align 4
--- /dev/null
+#as: -march=k8
+#source: nops-5.s
+#objdump: -drw
+#name: x86-64 -march=k8 nops 5
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <i386>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%rsi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%rdi,%riz,1\),%edi
+
+0+10 <i486>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%rsi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%rdi,%riz,1\),%edi
+
+0+20 <i586>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%rsi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%rdi,%riz,1\),%edi
+
+0+30 <i686>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\)
+
+0+40 <pentium4>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\)
+
+0+50 <nocona>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\)
+
+0+60 <core>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\)
+
+0+70 <core2>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\)
+
+0+80 <k6>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%rsi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%rdi,%riz,1\),%edi
+
+0+90 <athlon>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\)
+[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\)
+
+0+a0 <k8>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\)
+[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\)
+
+0+b0 <generic32>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%rsi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%rdi,%riz,1\),%edi
+
+0+c0 <generic64>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\)
+
+0+d0 <amdfam10>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\)
+[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\)
+#pass
--- /dev/null
+#source: nops-5.s
+#objdump: -drw
+#name: x86-64 nops 5
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <i386>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%rsi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%rdi,%riz,1\),%edi
+
+0+10 <i486>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%rsi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%rdi,%riz,1\),%edi
+
+0+20 <i586>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%rsi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%rdi,%riz,1\),%edi
+
+0+30 <i686>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\)
+
+0+40 <pentium4>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\)
+
+0+50 <nocona>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\)
+
+0+60 <core>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\)
+
+0+70 <core2>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\)
+
+0+80 <k6>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%rsi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%rdi,%riz,1\),%edi
+
+0+90 <athlon>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\)
+[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\)
+
+0+a0 <k8>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\)
+[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\)
+
+0+b0 <generic32>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 8d b6 00 00 00 00 lea 0x0\(%rsi\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%rdi,%riz,1\),%edi
+
+0+c0 <generic64>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\)
+
+0+d0 <amdfam10>:
+[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
+[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\)
+[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\)
+#pass
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