void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
-
switch (reg) {
case M68K_CR_CACR:
env->cacr = val;
break;
/* TODO: Implement control registers. */
default:
- cpu_abort(CPU(cpu),
+ cpu_abort(env_cpu(env),
"Unimplemented control register write 0x%x = 0x%x\n",
reg, val);
}
void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
-
switch (reg) {
/* MC680[1234]0 */
case M68K_CR_SFC:
env->mmu.ttr[M68K_DTTR1] = val;
return;
}
- cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x = 0x%x\n",
+ cpu_abort(env_cpu(env),
+ "Unimplemented control register write 0x%x = 0x%x\n",
reg, val);
}
uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
-
switch (reg) {
/* MC680[1234]0 */
case M68K_CR_SFC:
case M68K_CR_DTT1:
return env->mmu.ttr[M68K_DTTR1];
}
- cpu_abort(CPU(cpu), "Unimplemented control register read 0x%x\n",
+ cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n",
reg);
}
uint32_t last_logical, last_physical;
int32_t size;
int last_attr = -1, attr = -1;
- M68kCPU *cpu = m68k_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
MemTxResult txres;
if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
int *prot, target_ulong address,
int access_type, target_ulong *page_size)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
uint32_t entry;
uint32_t next;
target_ulong page_mask;
z = n; \
break; \
default: \
- cpu_abort(CPU(m68k_env_get_cpu(env)), "Bad CC_OP %d", op); \
+ cpu_abort(env_cpu(env), "Bad CC_OP %d", op); \
} \
} while (0)
#if defined(CONFIG_SOFTMMU)
void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
hwaddr physical;
int access_type;
int prot;
if (ret == 0) {
addr &= TARGET_PAGE_MASK;
physical += addr & (page_size - 1);
- tlb_set_page(cs, addr, physical,
+ tlb_set_page(env_cpu(env), addr, physical,
prot, access_type & ACCESS_SUPER ?
MMU_KERNEL_IDX : MMU_USER_IDX, page_size);
}
void HELPER(pflush)(CPUM68KState *env, uint32_t addr, uint32_t opmode)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
+ CPUState *cs = env_cpu(env);
switch (opmode) {
case 0: /* Flush page entry if not global */
case 1: /* Flush page entry */
- tlb_flush_page(CPU(cpu), addr);
+ tlb_flush_page(cs, addr);
break;
case 2: /* Flush all except global entries */
- tlb_flush(CPU(cpu));
+ tlb_flush(cs);
break;
case 3: /* Flush all entries */
- tlb_flush(CPU(cpu));
+ tlb_flush(cs);
break;
}
}
static void cf_interrupt_all(CPUM68KState *env, int is_hw)
{
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint32_t sp;
uint32_t sr;
uint32_t fmt;
{
if (m68k_feature(env, M68K_FEATURE_QUAD_MULDIV)) {
/* all except 68000 */
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
switch (format) {
case 4:
*sp -= 4;
static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
{
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint32_t sp;
uint32_t retaddr;
uint32_t vector;
static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
{
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = tt;
cpu_loop_exit_restore(cs, raddr);
env->cc_c = 0 <= ub ? val < 0 || val > ub : val > ub && val < 0;
if (val < 0 || val > ub) {
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
/* Recover PC and CC_OP for the beginning of the insn. */
cpu_restore_state(cs, GETPC(), true);
env->cc_c = lb <= ub ? val < lb || val > ub : val > ub && val < lb;
if (env->cc_c) {
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
/* Recover PC and CC_OP for the beginning of the insn. */
cpu_restore_state(cs, GETPC(), true);