Add MIPS32 as a seperate MIPS architecture

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 059827a..4c5b4cf 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,28 @@
+2000-12-01  Chris Demetriou  <cgd@sibyte.com>
+
+        * aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mips32 and
+        bfd_mach_mips32_4k.  Update FIXME comment.
+        * archures.c (bfd_mach_mips32): New constant.
+        (bfd_mach_mips4K, bfd_mach_mips32_4k) Rename the former to
+        the latter, renumber it.
+        * bfd-in2.h (bfd_mach_mips32): New constant.
+        (bfd_mach_mips4K, bfd_mach_mips32_4k) Rename the former to
+        the latter, renumber it.
+        * cpu-mips.c (I_mips32): New constant.
+        (I_mips4K, I_mips32_4k): Rename the former to the latter.
+        (arch_info_struct): Add bfd_mach_mips32 entry, replace
+        bfd_mach_mips4K entry with bfd_mach_mips32_4k entry.
+        * elf32-mips.c (elf_mips_isa): Add E_MIPS_ARCH_32 case.
+        (elf_mips_mach): Likewise.  Also, replace E_MIPS_MACH_MIPS32
+        with E_MIPS_MACH_MIPS32_4K.
+        (_bfd_mips_elf_final_write_processing): Replace
+        bfd_mach_mips4K with bfd_mach_mips32_4k case, add
+        bfd_mach_mips32 case.
+        (_bfd_mips_elf_merge_private_bfd_data): Generalize ISA mixing
+        comparison with support for MIPS32.
+        (_bfd_mips_elf_print_private_bfd_data): Print ISA name for
+        MIPS32.
+
 2000-12-01      Joel Sherrill <joel@OARcorp.com>
 
        * config.bfd (arm-*-rtems*, a29k-*rtems*): New targets.

diff --git a/bfd/aoutx.h b/bfd/aoutx.h
index a050b8b..388e8d7 100644 (file)
--- a/bfd/aoutx.h
+++ b/bfd/aoutx.h
@@ -776,7 +776,9 @@ NAME(aout,machine_type) (arch, machine, unknown)
     case bfd_mach_mips8000:
     case bfd_mach_mips10000:
     case bfd_mach_mips16:
-      /* FIXME: These should be MIPS3 or MIPS4.  */
+    case bfd_mach_mips32:
+    case bfd_mach_mips32_4k:
+      /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc.  */
       arch_flags = M_MIPS2;
       break;
     default:

diff --git a/bfd/archures.c b/bfd/archures.c
index 27a41b3..5bb4ff7 100644 (file)
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -130,8 +130,9 @@ DESCRIPTION
 .#define bfd_mach_mips6000             6000
 .#define bfd_mach_mips8000             8000
 .#define bfd_mach_mips10000            10000
-.#define bfd_mach_mips4K               32
 .#define bfd_mach_mips16               16
+.#define bfd_mach_mips32                32
+.#define bfd_mach_mips32_4k             3204113 {* 32, 04, octal 'K' *}
 .  bfd_arch_i386,      {* Intel 386 *}
 .#define bfd_mach_i386_i386 0
 .#define bfd_mach_i386_i8086 1

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 8120e24..0280f12 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1398,8 +1398,9 @@ enum bfd_architecture
 #define bfd_mach_mips6000              6000
 #define bfd_mach_mips8000              8000
 #define bfd_mach_mips10000             10000
-#define bfd_mach_mips4K                32
 #define bfd_mach_mips16                16
+#define bfd_mach_mips32                32
+#define bfd_mach_mips32_4k             3204113 /* 32, 04, octal 'K' */
   bfd_arch_i386,      /* Intel 386 */
 #define bfd_mach_i386_i386 0
 #define bfd_mach_i386_i8086 1

diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index e15af2e..0ac23cb 100644 (file)
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -38,26 +38,28 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
     NEXT,                                              \
   }
 
-enum {
-I_mips3000,
-I_mips3900,
-I_mips4000,
-I_mips4010,
-I_mips4100,
-I_mips4111,
-I_mips4300,
-I_mips4400,
-I_mips4600,
-I_mips4650,
-I_mips5000,
-I_mips6000,
-I_mips8000,
-I_mips10000,
-I_mips4K,
-I_mips16
+enum
+{
+  I_mips3000,
+  I_mips3900,
+  I_mips4000,
+  I_mips4010,
+  I_mips4100,
+  I_mips4111,
+  I_mips4300,
+  I_mips4400,
+  I_mips4600,
+  I_mips4650,
+  I_mips5000,
+  I_mips6000,
+  I_mips8000,
+  I_mips10000,
+  I_mips16,
+  I_mips32,
+  I_mips32_4k,
 };
 
-#define NN(index) (&arch_info_struct[(index)+1])
+#define NN(index) (&arch_info_struct[(index) + 1])
 
 static const bfd_arch_info_type arch_info_struct[] =
 {
@@ -74,9 +76,10 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mips5000, "mips:5000", false, NN(I_mips5000)),
   N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
   N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
-  N (64, 64, bfd_mach_mips10000, "mips:10000", false, NN(I_mips10000)),
-  N (32, 32, bfd_mach_mips4K,   "mips:4K",   false, NN(I_mips4K)),
-  N (64, 64, bfd_mach_mips16,   "mips:16",   false, 0),
+  N (64, 64, bfd_mach_mips10000,"mips:10000",false, NN(I_mips10000)),
+  N (64, 64, bfd_mach_mips16,   "mips:16",   false, NN(I_mips16)),
+  N (32, 32, bfd_mach_mips32,   "mips:mips32", false, NN(I_mips32)),
+  N (32, 32, bfd_mach_mips32_4k,"mips:mips32-4k", false, 0),
 };
 
 /* The default architecture is mips:3000, but with a machine number of

diff --git a/bfd/elf32-mips.c b/bfd/elf32-mips.c
index b9b99c7..b58eddf 100644 (file)
--- a/bfd/elf32-mips.c
+++ b/bfd/elf32-mips.c
@@ -1810,6 +1810,8 @@ elf_mips_isa (flags)
       return 3;
     case E_MIPS_ARCH_4:
       return 4;
+    case E_MIPS_ARCH_32:
+      return 32;
     }
   return 4;
 }
@@ -1837,8 +1839,8 @@ elf_mips_mach (flags)
     case E_MIPS_MACH_4650:
       return bfd_mach_mips4650;
 
-    case E_MIPS_MACH_MIPS32:
-      return bfd_mach_mips4K;
+    case E_MIPS_MACH_MIPS32_4K:
+      return bfd_mach_mips32_4k;
 
     default:
       switch (flags & EF_MIPS_ARCH)
@@ -1859,6 +1861,10 @@ elf_mips_mach (flags)
        case E_MIPS_ARCH_4:
          return bfd_mach_mips8000;
          break;
+
+       case E_MIPS_ARCH_32:
+         return bfd_mach_mips32;
+         break;
        }
     }
 
@@ -2336,8 +2342,12 @@ _bfd_mips_elf_final_write_processing (abfd, linker)
       val = E_MIPS_ARCH_4;
       break;
 
-    case bfd_mach_mips4K:
-      val = E_MIPS_ARCH_2 | E_MIPS_MACH_MIPS32;
+    case bfd_mach_mips32:
+      val = E_MIPS_ARCH_32;
+      break;
+
+    case bfd_mach_mips32_4k:
+      val = E_MIPS_ARCH_32 | E_MIPS_MACH_MIPS32_4K;
       break;
     }
 
@@ -2537,13 +2547,12 @@ _bfd_mips_elf_merge_private_bfd_data (ibfd, obfd)
          || new_mach == old_mach
          )
        {
-         /* Don't warn about mixing -mips1 and -mips2 code, or mixing -mips3
-            and -mips4 code.  They will normally use the same data sizes and
-            calling conventions.  */
+         /* Don't warn about mixing code using 32-bit ISAs, or mixing code
+            using 64-bit ISAs.  They will normally use the same data sizes
+            and calling conventions.  */
 
-         if ((new_isa == 1 || new_isa == 2)
-             ? (old_isa != 1 && old_isa != 2)
-             : (old_isa == 1 || old_isa == 2))
+         if ((  (new_isa == 1 || new_isa == 2 || new_isa == 32)
+              ^ (old_isa == 1 || old_isa == 2 || old_isa == 32)) != 0)
            {
              (*_bfd_error_handler)
               (_("%s: ISA mismatch (-mips%d) with previous modules (-mips%d)"),
@@ -2647,6 +2656,8 @@ _bfd_mips_elf_print_private_bfd_data (abfd, ptr)
     fprintf (file, _(" [mips3]"));
   else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
     fprintf (file, _(" [mips4]"));
+  else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32)
+    fprintf (file, _ (" [mips32]"));
   else
     fprintf (file, _(" [unknown ISA]"));
 

diff --git a/bfd/po/POTFILES.in b/bfd/po/POTFILES.in
index 3134225..f75b4ca 100644 (file)
--- a/bfd/po/POTFILES.in
+++ b/bfd/po/POTFILES.in
@@ -136,7 +136,6 @@ elf64.c
 elf64-gen.c
 elf64-hppa.c
 elf64-hppa.h
-elf64-ia64.c
 elf64-mips.c
 elf64-sparc.c
 elf64-x86-64.c

diff --git a/bfd/po/bfd.pot b/bfd/po/bfd.pot
index 9f84596..2534d97 100644 (file)
--- a/bfd/po/bfd.pot
+++ b/bfd/po/bfd.pot
@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2000-11-30 11:08-0800\n"
+"POT-Creation-Date: 2000-12-01 13:12-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -34,22 +34,22 @@ msgstr ""
 msgid "%s: Bad relocation record imported: %d"
 msgstr ""
 
-#: aoutx.h:1254 aoutx.h:1668
+#: aoutx.h:1256 aoutx.h:1670
 #, c-format
 msgid "%s: can not represent section `%s' in a.out object file format"
 msgstr ""
 
-#: aoutx.h:1638
+#: aoutx.h:1640
 #, c-format
 msgid ""
 "%s: can not represent section for symbol `%s' in a.out object file format"
 msgstr ""
 
-#: aoutx.h:1640
+#: aoutx.h:1642
 msgid "*unknown*"
 msgstr ""
 
-#: aoutx.h:3679
+#: aoutx.h:3681
 #, c-format
 msgid "%s: relocateable link from %s to %s not supported"
 msgstr ""
@@ -660,7 +660,7 @@ msgstr ""
 
 #. Ignore init flag - it may not be set, despite the flags field
 #. containing valid data.
-#: elf32-arm.h:2195 elf32-cris.c:615 elf32-m68k.c:430 elf32-mips.c:2623
+#: elf32-arm.h:2195 elf32-cris.c:615 elf32-m68k.c:430 elf32-mips.c:2632
 #, c-format
 msgid "private flags = %lx:"
 msgstr ""
@@ -803,7 +803,7 @@ msgstr ""
 msgid "SDA relocation when _SDA_BASE_ not defined"
 msgstr ""
 
-#: elf32-m32r.c:1000 elf32-ppc.c:2973 elf64-ia64.c:3256
+#: elf32-m32r.c:1000 elf32-ppc.c:2973
 #, c-format
 msgid "%s: unknown relocation type %d"
 msgstr ""
@@ -854,120 +854,124 @@ msgstr ""
 msgid "Linking mips16 objects into %s format is not supported"
 msgstr ""
 
-#: elf32-mips.c:2509
+#: elf32-mips.c:2519
 #, c-format
 msgid "%s: linking PIC files with non-PIC files"
 msgstr ""
 
-#: elf32-mips.c:2519
+#: elf32-mips.c:2529
 #, c-format
 msgid "%s: linking abicalls files with non-abicalls files"
 msgstr ""
 
-#: elf32-mips.c:2549
+#: elf32-mips.c:2558
 #, c-format
 msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)"
 msgstr ""
 
-#: elf32-mips.c:2558
+#: elf32-mips.c:2567
 #, c-format
 msgid "%s: ISA mismatch (%d) with previous modules (%d)"
 msgstr ""
 
-#: elf32-mips.c:2581
+#: elf32-mips.c:2590
 #, c-format
 msgid "%s: ABI mismatch: linking %s module with previous %s modules"
 msgstr ""
 
-#: elf32-mips.c:2595 elf32-ppc.c:1481 elf64-sparc.c:2974
+#: elf32-mips.c:2604 elf32-ppc.c:1481 elf64-sparc.c:2974
 #, c-format
 msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
 msgstr ""
 
-#: elf32-mips.c:2626
+#: elf32-mips.c:2635
 msgid " [abi=O32]"
 msgstr ""
 
-#: elf32-mips.c:2628
+#: elf32-mips.c:2637
 msgid " [abi=O64]"
 msgstr ""
 
-#: elf32-mips.c:2630
+#: elf32-mips.c:2639
 msgid " [abi=EABI32]"
 msgstr ""
 
-#: elf32-mips.c:2632
+#: elf32-mips.c:2641
 msgid " [abi=EABI64]"
 msgstr ""
 
-#: elf32-mips.c:2634
+#: elf32-mips.c:2643
 msgid " [abi unknown]"
 msgstr ""
 
-#: elf32-mips.c:2636
+#: elf32-mips.c:2645
 msgid " [abi=N32]"
 msgstr ""
 
-#: elf32-mips.c:2638
+#: elf32-mips.c:2647
 msgid " [abi=64]"
 msgstr ""
 
-#: elf32-mips.c:2640
+#: elf32-mips.c:2649
 msgid " [no abi set]"
 msgstr ""
 
-#: elf32-mips.c:2643
+#: elf32-mips.c:2652
 msgid " [mips1]"
 msgstr ""
 
-#: elf32-mips.c:2645
+#: elf32-mips.c:2654
 msgid " [mips2]"
 msgstr ""
 
-#: elf32-mips.c:2647
+#: elf32-mips.c:2656
 msgid " [mips3]"
 msgstr ""
 
-#: elf32-mips.c:2649
+#: elf32-mips.c:2658
 msgid " [mips4]"
 msgstr ""
 
-#: elf32-mips.c:2651
+#: elf32-mips.c:2660
+msgid " [mips32]"
+msgstr ""
+
+#: elf32-mips.c:2662
 msgid " [unknown ISA]"
 msgstr ""
 
-#: elf32-mips.c:2654
+#: elf32-mips.c:2665
 msgid " [32bitmode]"
 msgstr ""
 
-#: elf32-mips.c:2656
+#: elf32-mips.c:2667
 msgid " [not 32bitmode]"
 msgstr ""
 
-#: elf32-mips.c:4305
+#: elf32-mips.c:4316
 msgid "static procedure (no name)"
 msgstr ""
 
-#: elf32-mips.c:4920 elf64-alpha.c:4378
+#: elf32-mips.c:4931 elf64-alpha.c:4378
 #, c-format
 msgid "%s: illegal section name `%s'"
 msgstr ""
 
-#: elf32-mips.c:5484
+#: elf32-mips.c:5495
 msgid "not enough GOT space for local GOT entries"
 msgstr ""
 
-#: elf32-mips.c:6601
+#: elf32-mips.c:6612
 #, c-format
 msgid "%s: %s+0x%lx: jump to stub routine which is not jal"
 msgstr ""
 
-#: elf32-mips.c:7588
+#: elf32-mips.c:7599
 #, c-format
 msgid "Malformed reloc detected for section %s"
 msgstr ""
 
-#: elf32-mips.c:7665
+#: elf32-mips.c:7676
 #, c-format
 msgid "%s: CALL16 reloc at 0x%lx not against global symbol"
 msgstr ""
@@ -1141,73 +1145,6 @@ msgstr ""
 msgid "%s: .got subsegment exceeds 64K (size %d)"
 msgstr ""
 
-#: elf64-ia64.c:1839
-msgid "@pltoff reloc against local symbol"
-msgstr ""
-
-#: elf64-ia64.c:1886
-msgid "non-zero addend in @fptr reloc"
-msgstr ""
-
-#: elf64-ia64.c:3103
-#, c-format
-msgid "%s: short data segment overflowed (0x%lx >= 0x400000)"
-msgstr ""
-
-#: elf64-ia64.c:3114
-#, c-format
-msgid "%s: __gp does not cover short data segment"
-msgstr ""
-
-#: elf64-ia64.c:3407
-#, c-format
-msgid "%s: linking non-pic code in a shared library"
-msgstr ""
-
-#: elf64-ia64.c:3437
-#, c-format
-msgid "%s: @gprel relocation against dynamic symbol %s"
-msgstr ""
-
-#: elf64-ia64.c:3573
-#, c-format
-msgid "%s: dynamic relocation against speculation fixup"
-msgstr ""
-
-#: elf64-ia64.c:3581
-#, c-format
-msgid "%s: speculation fixup against undefined weak symbol"
-msgstr ""
-
-#: elf64-ia64.c:3738
-msgid "unsupported reloc"
-msgstr ""
-
-#: elf64-ia64.c:4056
-#, c-format
-msgid "%s: linking trap-on-NULL-dereference with non-trapping files"
-msgstr ""
-
-#: elf64-ia64.c:4065
-#, c-format
-msgid "%s: linking big-endian files with little-endian files"
-msgstr ""
-
-#: elf64-ia64.c:4074
-#, c-format
-msgid "%s: linking 64-bit files with 32-bit files"
-msgstr ""
-
-#: elf64-ia64.c:4083
-#, c-format
-msgid "%s: linking constant-gp files with non-constant-gp files"
-msgstr ""
-
-#: elf64-ia64.c:4093
-#, c-format
-msgid "%s: linking auto-pic files with non-auto-pic files"
-msgstr ""
-
 #: elf64-sparc.c:1250
 #, c-format
 msgid "%s: check_relocs: unhandled reloc type %d"

diff --git a/config.sub b/config.sub
index af79d70..f8d46e4 100755 (executable)
--- a/config.sub
+++ b/config.sub
@@ -211,10 +211,11 @@ esac
 case $basic_machine in
        # Recognize the basic CPU types without company name.
        # Some are omitted here because they have special meanings below.
-       tahoe | i860 | ia64 | m32r | m68k | m68000 | m88k | ns32k | arc | arm \
-               | arme[lb] | armv[2345] | armv[345][lb] | pyramid | mn10200 | mn10300 | tron | a29k \
+       tahoe | i860 | ia64 | m32r | m68k | m68000 | m88k | ns32k | arc \
+               | arm | arme[lb] | arm[bl]e | armv[2345] | armv[345][lb] | strongarm | xscale \
+               | pyramid | mn10200 | mn10300 | tron | a29k \
                | 580 | i960 | h8300 \
-               | x86 | ppcbe | mipsbe | mipsle | shbe | shle | armbe | armle \
+               | x86 | ppcbe | mipsbe | mipsle | shbe | shle \
                | hppa | hppa1.0 | hppa1.1 | hppa2.0 | hppa2.0w | hppa2.0n \
                | hppa64 \
                | alpha | alphaev[4-8] | alphaev56 | alphapca5[67] \
@@ -251,11 +252,12 @@ case $basic_machine in
        # Recognize the basic CPU types with company name.
        # FIXME: clean up the formatting here.
        vax-* | tahoe-* | i[234567]86-* | i860-* | ia64-* | m32r-* | m68k-* | m68000-* \
-             | m88k-* | sparc-* | ns32k-* | fx80-* | arc-* | arm-* | c[123]* \
+             | m88k-* | sparc-* | ns32k-* | fx80-* | arc-* | c[123]* \
+             | arm-*  | armbe-* | armle-* | armv*-* | strongarm-* | xscale-* \
              | mips-* | pyramid-* | tron-* | a29k-* | romp-* | rs6000-* \
              | power-* | none-* | 580-* | cray2-* | h8300-* | h8500-* | i960-* \
              | xmp-* | ymp-* \
-             | x86-* | ppcbe-* | mipsbe-* | mipsle-* | shbe-* | shle-* | armbe-* | armle-* \
+             | x86-* | ppcbe-* | mipsbe-* | mipsle-* | shbe-* | shle-* \
              | hppa-* | hppa1.0-* | hppa1.1-* | hppa2.0-* | hppa2.0w-* \
              | hppa2.0n-* | hppa64-* \
              | alpha-* | alphaev[4-8]-* | alphaev56-* | alphapca5[67]-* \
@@ -267,7 +269,7 @@ case $basic_machine in
              | mips64el-* | mips64orion-* | mips64orionel-* \
              | mips64vr4100-* | mips64vr4100el-* | mips64vr4300-* | mips64vr4300el-* \
              | mipstx39-* | mipstx39el-* | mcore-* \
-             | f301-* | armv*-* | s390-* | sv1-* | t3e-* \
+             | f301-* | s390-* | sv1-* | t3e-* \
              | m88110-* | m680[01234]0-* | m683?2-* | m68360-* | z8k-* | d10v-* \
              | thumb-* | v850-* | d30v-* | tic30-* | c30-* | fr30-* \
              | bs2000-* | tic54x-* | c54x-* | x86_64-*)

diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index aa2d4e0..a1ef885 100644 (file)
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,9 @@
+2000-10-16  Chris Demetriou  <cgd@sibyte.com>
+
+        * mips.h (E_MIPS_ARCH_32): New constant.
+        (E_MIPS_MACH_MIPS32, E_MIPS_MACH_MIPS32_4K): Replace the
+        former with the latter. 
+
 2000-11-30  Jan Hubicka  <jh@suse.cz>
        
         * common.h (EM_X86_64): New macro.

diff --git a/include/elf/mips.h b/include/elf/mips.h
index 18185e7..41f52cd 100644 (file)
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -121,6 +121,9 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 /* -mips4 code.  */
 #define E_MIPS_ARCH_4          0x30000000
 
+/* -mips32 code.  */
+#define E_MIPS_ARCH_32                0x50000000
+
 /* The ABI of the file.  Also see EF_MIPS_ABI2 above. */
 #define EF_MIPS_ABI            0x0000F000
 
@@ -153,9 +156,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_4100       0x00830000
 #define E_MIPS_MACH_4650       0x00850000
 #define E_MIPS_MACH_4111       0x00880000
-/* -mips32 code.
-   It is easier to treat MIPS32 as a machine rather than an architecture.  */
-#define E_MIPS_MACH_MIPS32     0x00890000
+#define E_MIPS_MACH_MIPS32_4K  0x00890000
 \f
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 902544a..ceb0317 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -8,6 +8,23 @@
         (MIPS operand specifier comments): Remove 'm', add 'U' and
         'J', and update the meaning of 'B' so that it's more general.
 
+        * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
+        INSN_ISA5): Renumber, redefine to mean the ISA at which the
+        instruction was added.
+        (INSN_ISA32): New constant.
+        (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
+        Renumber to avoid new and/or renumbered INSN_* constants.
+        (INSN_MIPS32): Delete.
+        (ISA_UNKNOWN): New constant to indicate unknown ISA.
+        (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
+        ISA_MIPS32): New constants, defined to be the mask of INSN_*
+        constants available at that ISA level. 
+        (CPU_UNKNOWN): New constant to indicate unknown CPU.
+        (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
+        define it with a unique value.
+        (OPCODE_IS_MEMBER): Update for new ISA membership-related
+        constant meanings.
+
 2000-10-20  Jakub Jelinek  <jakub@redhat.com>
 
        * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 61931f6..7eaba30 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -302,41 +302,43 @@ struct mips_opcode
    disassembler, and requires special treatment by the assembler.  */
 #define INSN_MACRO                  0xffffffff
 
-
-
-
-
-/* MIPS ISA field--CPU level at which insn is supported.  */
-#define INSN_ISA                   0x0000000F
-/* An instruction which is not part of any basic MIPS ISA.
-   (ie it is a chip specific instruction)  */
-#define INSN_NO_ISA                0x00000000
-/* MIPS ISA 1 instruction.  */
-#define INSN_ISA1                  0x00000001
-/* MIPS ISA 2 instruction (R6000 or R4000).  */
-#define INSN_ISA2                  0x00000002
-/* MIPS ISA 3 instruction (R4000).  */
-#define INSN_ISA3                  0x00000003
-/* MIPS ISA 4 instruction (R8000).  */
-#define INSN_ISA4                  0x00000004
-#define INSN_ISA5                  0x00000005
+/* Masks used to mark instructions to indicate which MIPS ISA level
+   they were introduced in.  ISAs, as defined below, are logical
+   ORs of these bits, indicatingthat they support the instructions
+   defined at the given level.  */
+
+#define INSN_ISA1                 0x00000010
+#define INSN_ISA2                 0x00000020
+#define INSN_ISA3                 0x00000040
+#define INSN_ISA4                 0x00000080
+#define INSN_ISA5                 0x00000100
+#define INSN_ISA32                0x00000200
 
 /* Chip specific instructions.  These are bitmasks.  */
+
 /* MIPS R4650 instruction.  */
-#define INSN_4650                  0x00000010
+#define INSN_4650                 0x00010000
 /* LSI R4010 instruction.  */
-#define INSN_4010                  0x00000020
-/* NEC VR4100 instruction. */
-#define INSN_4100                   0x00000040
+#define INSN_4010                 0x00020000
+/* NEC VR4100 instruction.  */
+#define INSN_4100                   0x00040000
 /* Toshiba R3900 instruction.  */
-#define INSN_3900                   0x00000080
-/* MIPS32 instruction (4Kc, 4Km, 4Kp).  */
-#define INSN_MIPS32                 0x00000100
-/* 32-bit code running on a ISA3+ CPU. */
-#define INSN_GP32                   0x00001000
+#define INSN_3900                   0x00080000
+/* 32-bit code running on a ISA3+ CPU.  */
+#define INSN_GP32                   0x00100000
+
+/* MIPS ISA defines, use instead of hardcoding ISA level.  */
+
+#define       ISA_UNKNOWN     0               /* Gas internal use.  */
+#define       ISA_MIPS1       (INSN_ISA1)
+#define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
+#define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
+#define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
+#define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 
 /* CPU defines, use instead of hardcoding processor number. Keep this
    in sync with bfd/archures.c in order for machine selection to work.  */
+#define CPU_UNKNOWN    0               /* Gas internal use.  */
 #define CPU_R2000      2000
 #define CPU_R3000      3000
 #define CPU_R3900      3900
@@ -354,7 +356,7 @@ struct mips_opcode
 #define CPU_R10000     10000
 #define CPU_MIPS16     16
 #define CPU_MIPS32     32
-#define CPU_4K         CPU_MIPS32
+#define CPU_MIPS32_4K  3204113         /* 32, 04, octal 'K' */
 
 /* Test for membership in an ISA including chip specific ISAs.
    INSN is pointer to an element of the opcode table; ISA is the
@@ -365,236 +367,235 @@ struct mips_opcode
    in the MIPS gas docs. */
 
 #define OPCODE_IS_MEMBER(insn, isa, cpu, gp32)                         \
-    ((((insn)->membership & INSN_ISA) != 0                             \
-      && ((insn)->membership & INSN_ISA) <= (unsigned) isa             \
+    ((((insn)->membership & isa) != 0                                  \
       && ((insn)->membership & INSN_GP32 ? gp32 : 1))                  \
      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)    \
      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)    \
      || ((cpu == CPU_VR4100 || cpu == CPU_R4111)                       \
         && ((insn)->membership & INSN_4100) != 0)                      \
-     || (cpu == CPU_MIPS32 && ((insn)->membership & INSN_MIPS32) != 0) \
      || (cpu == CPU_R3900  && ((insn)->membership & INSN_3900) != 0))
 
 /* This is a list of macro expanded instructions.
- *
- * _I appended means immediate
- * _A appended means address
- * _AB appended means address with base register
- * _D appended means 64 bit floating point constant
- * _S appended means 32 bit floating point constant
- */
-enum {
-    M_ABS,
-    M_ADD_I,
-    M_ADDU_I,
-    M_AND_I,
-    M_BEQ,
-    M_BEQ_I,
-    M_BEQL_I,
-    M_BGE,
-    M_BGEL,
-    M_BGE_I,
-    M_BGEL_I,
-    M_BGEU,
-    M_BGEUL,
-    M_BGEU_I,
-    M_BGEUL_I,
-    M_BGT,
-    M_BGTL,
-    M_BGT_I,
-    M_BGTL_I,
-    M_BGTU,
-    M_BGTUL,
-    M_BGTU_I,
-    M_BGTUL_I,
-    M_BLE,
-    M_BLEL,
-    M_BLE_I,
-    M_BLEL_I,
-    M_BLEU,
-    M_BLEUL,
-    M_BLEU_I,
-    M_BLEUL_I,
-    M_BLT,
-    M_BLTL,
-    M_BLT_I,
-    M_BLTL_I,
-    M_BLTU,
-    M_BLTUL,
-    M_BLTU_I,
-    M_BLTUL_I,
-    M_BNE,
-    M_BNE_I,
-    M_BNEL_I,
-    M_DABS,
-    M_DADD_I,
-    M_DADDU_I,
-    M_DDIV_3,
-    M_DDIV_3I,
-    M_DDIVU_3,
-    M_DDIVU_3I,
-    M_DIV_3,
-    M_DIV_3I,
-    M_DIVU_3,
-    M_DIVU_3I,
-    M_DLA_AB,
-    M_DLI,
-    M_DMUL,
-    M_DMUL_I, 
-    M_DMULO,
-    M_DMULO_I, 
-    M_DMULOU,
-    M_DMULOU_I, 
-    M_DREM_3,
-    M_DREM_3I,
-    M_DREMU_3,
-    M_DREMU_3I,
-    M_DSUB_I,
-    M_DSUBU_I,
-    M_DSUBU_I_2,
-    M_J_A,
-    M_JAL_1,
-    M_JAL_2,
-    M_JAL_A,
-    M_L_DOB,
-    M_L_DAB,
-    M_LA_AB,
-    M_LB_A,
-    M_LB_AB,
-    M_LBU_A,
-    M_LBU_AB,
-    M_LD_A,
-    M_LD_OB,
-    M_LD_AB,
-    M_LDC1_AB,
-    M_LDC2_AB,
-    M_LDC3_AB,
-    M_LDL_AB,
-    M_LDR_AB,
-    M_LH_A,
-    M_LH_AB,
-    M_LHU_A,
-    M_LHU_AB,
-    M_LI,
-    M_LI_D,
-    M_LI_DD,
-    M_LI_S,
-    M_LI_SS,
-    M_LL_AB,
-    M_LLD_AB,
-    M_LS_A,
-    M_LW_A,
-    M_LW_AB,
-    M_LWC0_A,
-    M_LWC0_AB,
-    M_LWC1_A,
-    M_LWC1_AB,
-    M_LWC2_A,
-    M_LWC2_AB,
-    M_LWC3_A,
-    M_LWC3_AB,
-    M_LWL_A,
-    M_LWL_AB,
-    M_LWR_A,
-    M_LWR_AB,
-    M_LWU_AB,
-    M_MUL,
-    M_MUL_I, 
-    M_MULO,
-    M_MULO_I, 
-    M_MULOU,
-    M_MULOU_I, 
-    M_NOR_I,
-    M_OR_I,
-    M_REM_3,
-    M_REM_3I,
-    M_REMU_3,
-    M_REMU_3I,
-    M_ROL,
-    M_ROL_I,
-    M_ROR,
-    M_ROR_I,
-    M_S_DA,
-    M_S_DOB,
-    M_S_DAB,
-    M_S_S,
-    M_SC_AB,
-    M_SCD_AB,
-    M_SD_A,
-    M_SD_OB,
-    M_SD_AB,
-    M_SDC1_AB,
-    M_SDC2_AB,
-    M_SDC3_AB,
-    M_SDL_AB,
-    M_SDR_AB,
-    M_SEQ,
-    M_SEQ_I,
-    M_SGE,
-    M_SGE_I,
-    M_SGEU,
-    M_SGEU_I,
-    M_SGT,
-    M_SGT_I,
-    M_SGTU,
-    M_SGTU_I,
-    M_SLE,
-    M_SLE_I,
-    M_SLEU,
-    M_SLEU_I,
-    M_SLT_I,
-    M_SLTU_I,
-    M_SNE,
-    M_SNE_I,
-    M_SB_A,
-    M_SB_AB,
-    M_SH_A,
-    M_SH_AB,
-    M_SW_A,
-    M_SW_AB,
-    M_SWC0_A,
-    M_SWC0_AB,
-    M_SWC1_A,
-    M_SWC1_AB,
-    M_SWC2_A,
-    M_SWC2_AB,
-    M_SWC3_A,
-    M_SWC3_AB,
-    M_SWL_A,
-    M_SWL_AB,
-    M_SWR_A,
-    M_SWR_AB,
-    M_SUB_I,
-    M_SUBU_I,
-    M_SUBU_I_2,
-    M_TEQ_I,
-    M_TGE_I,
-    M_TGEU_I,
-    M_TLT_I,
-    M_TLTU_I,
-    M_TNE_I,
-    M_TRUNCWD,
-    M_TRUNCWS,
-    M_ULD,
-    M_ULD_A,
-    M_ULH,
-    M_ULH_A,
-    M_ULHU,
-    M_ULHU_A,
-    M_ULW,
-    M_ULW_A,
-    M_USH,
-    M_USH_A,
-    M_USW,
-    M_USW_A,
-    M_USD,
-    M_USD_A,
-    M_XOR_I,
-    M_COP0,
-    M_COP1,
-    M_COP2,
-    M_COP3,
-    M_NUM_MACROS
+  
+   _I appended means immediate
+   _A appended means address
+   _AB appended means address with base register
+   _D appended means 64 bit floating point constant
+   _S appended means 32 bit floating point constant.  */
+
+enum
+{
+  M_ABS,
+  M_ADD_I,
+  M_ADDU_I,
+  M_AND_I,
+  M_BEQ,
+  M_BEQ_I,
+  M_BEQL_I,
+  M_BGE,
+  M_BGEL,
+  M_BGE_I,
+  M_BGEL_I,
+  M_BGEU,
+  M_BGEUL,
+  M_BGEU_I,
+  M_BGEUL_I,
+  M_BGT,
+  M_BGTL,
+  M_BGT_I,
+  M_BGTL_I,
+  M_BGTU,
+  M_BGTUL,
+  M_BGTU_I,
+  M_BGTUL_I,
+  M_BLE,
+  M_BLEL,
+  M_BLE_I,
+  M_BLEL_I,
+  M_BLEU,
+  M_BLEUL,
+  M_BLEU_I,
+  M_BLEUL_I,
+  M_BLT,
+  M_BLTL,
+  M_BLT_I,
+  M_BLTL_I,
+  M_BLTU,
+  M_BLTUL,
+  M_BLTU_I,
+  M_BLTUL_I,
+  M_BNE,
+  M_BNE_I,
+  M_BNEL_I,
+  M_DABS,
+  M_DADD_I,
+  M_DADDU_I,
+  M_DDIV_3,
+  M_DDIV_3I,
+  M_DDIVU_3,
+  M_DDIVU_3I,
+  M_DIV_3,
+  M_DIV_3I,
+  M_DIVU_3,
+  M_DIVU_3I,
+  M_DLA_AB,
+  M_DLI,
+  M_DMUL,
+  M_DMUL_I, 
+  M_DMULO,
+  M_DMULO_I, 
+  M_DMULOU,
+  M_DMULOU_I, 
+  M_DREM_3,
+  M_DREM_3I,
+  M_DREMU_3,
+  M_DREMU_3I,
+  M_DSUB_I,
+  M_DSUBU_I,
+  M_DSUBU_I_2,
+  M_J_A,
+  M_JAL_1,
+  M_JAL_2,
+  M_JAL_A,
+  M_L_DOB,
+  M_L_DAB,
+  M_LA_AB,
+  M_LB_A,
+  M_LB_AB,
+  M_LBU_A,
+  M_LBU_AB,
+  M_LD_A,
+  M_LD_OB,
+  M_LD_AB,
+  M_LDC1_AB,
+  M_LDC2_AB,
+  M_LDC3_AB,
+  M_LDL_AB,
+  M_LDR_AB,
+  M_LH_A,
+  M_LH_AB,
+  M_LHU_A,
+  M_LHU_AB,
+  M_LI,
+  M_LI_D,
+  M_LI_DD,
+  M_LI_S,
+  M_LI_SS,
+  M_LL_AB,
+  M_LLD_AB,
+  M_LS_A,
+  M_LW_A,
+  M_LW_AB,
+  M_LWC0_A,
+  M_LWC0_AB,
+  M_LWC1_A,
+  M_LWC1_AB,
+  M_LWC2_A,
+  M_LWC2_AB,
+  M_LWC3_A,
+  M_LWC3_AB,
+  M_LWL_A,
+  M_LWL_AB,
+  M_LWR_A,
+  M_LWR_AB,
+  M_LWU_AB,
+  M_MUL,
+  M_MUL_I, 
+  M_MULO,
+  M_MULO_I, 
+  M_MULOU,
+  M_MULOU_I, 
+  M_NOR_I,
+  M_OR_I,
+  M_REM_3,
+  M_REM_3I,
+  M_REMU_3,
+  M_REMU_3I,
+  M_ROL,
+  M_ROL_I,
+  M_ROR,
+  M_ROR_I,
+  M_S_DA,
+  M_S_DOB,
+  M_S_DAB,
+  M_S_S,
+  M_SC_AB,
+  M_SCD_AB,
+  M_SD_A,
+  M_SD_OB,
+  M_SD_AB,
+  M_SDC1_AB,
+  M_SDC2_AB,
+  M_SDC3_AB,
+  M_SDL_AB,
+  M_SDR_AB,
+  M_SEQ,
+  M_SEQ_I,
+  M_SGE,
+  M_SGE_I,
+  M_SGEU,
+  M_SGEU_I,
+  M_SGT,
+  M_SGT_I,
+  M_SGTU,
+  M_SGTU_I,
+  M_SLE,
+  M_SLE_I,
+  M_SLEU,
+  M_SLEU_I,
+  M_SLT_I,
+  M_SLTU_I,
+  M_SNE,
+  M_SNE_I,
+  M_SB_A,
+  M_SB_AB,
+  M_SH_A,
+  M_SH_AB,
+  M_SW_A,
+  M_SW_AB,
+  M_SWC0_A,
+  M_SWC0_AB,
+  M_SWC1_A,
+  M_SWC1_AB,
+  M_SWC2_A,
+  M_SWC2_AB,
+  M_SWC3_A,
+  M_SWC3_AB,
+  M_SWL_A,
+  M_SWL_AB,
+  M_SWR_A,
+  M_SWR_AB,
+  M_SUB_I,
+  M_SUBU_I,
+  M_SUBU_I_2,
+  M_TEQ_I,
+  M_TGE_I,
+  M_TGEU_I,
+  M_TLT_I,
+  M_TLTU_I,
+  M_TNE_I,
+  M_TRUNCWD,
+  M_TRUNCWS,
+  M_ULD,
+  M_ULD_A,
+  M_ULH,
+  M_ULH_A,
+  M_ULHU,
+  M_ULHU_A,
+  M_ULW,
+  M_ULW_A,
+  M_USH,
+  M_USH_A,
+  M_USW,
+  M_USW_A,
+  M_USD,
+  M_USD_A,
+  M_XOR_I,
+  M_COP0,
+  M_COP1,
+  M_COP2,
+  M_COP3,
+  M_NUM_MACROS
 };
 
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6bac17d..a03baa3 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -17,6 +17,14 @@
         MIPS32 "sdbbp" to use 'B' operand specifier.  Add MIPS32
         "wait" variant which uses 'J' operand specifier.
         
+        * mips-dis.c (set_mips_isa_type): Update to use
+        CPU_UNKNOWN and ISA_* constants.  Add bfd_mach_mips32 case.
+        Replace bfd_mach_mips4K with bfd_mach_mips32_4k case.
+        * mips-opc.c (I32): New constant for instructions added in
+        MIPS32.
+        (P4): Delete.
+        (mips_builtin_opcodes) Replace all uses of P4 with I32.
+
 2000-11-28  Hans-Peter Nilsson  <hp@bitrange.com>
 
        * sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned.

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 39bcf33..bb970ef 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -287,8 +287,8 @@ set_mips_isa_type (mach, isa, cputype)
      int *isa;
      int *cputype;
 {
-  int target_processor = 0;
-  int mips_isa = 0;
+  int target_processor = CPU_UNKNOWN;
+  int mips_isa = ISA_UNKNOWN;
 
   /* Use standard MIPS register names by default.  */
   reg_names = std_reg_names;
@@ -297,71 +297,75 @@ set_mips_isa_type (mach, isa, cputype)
     {
     case bfd_mach_mips3000:
       target_processor = CPU_R3000;
-      mips_isa = 1;
+      mips_isa = ISA_MIPS1;
       break;
     case bfd_mach_mips3900:
       target_processor = CPU_R3900;
-      mips_isa = 1;
+      mips_isa = ISA_MIPS1;
       break;
     case bfd_mach_mips4000:
       target_processor = CPU_R4000;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips4010:
       target_processor = CPU_R4010;
-      mips_isa = 2;
+      mips_isa = ISA_MIPS2;
       break;
     case bfd_mach_mips4100:
       target_processor = CPU_VR4100;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips4111:
       target_processor = CPU_VR4100; /* FIXME: Shouldn't this be CPU_R4111 ??? */
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips4300:
       target_processor = CPU_R4300;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips4400:
       target_processor = CPU_R4400;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips4600:
       target_processor = CPU_R4600;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips4650:
       target_processor = CPU_R4650;
-      mips_isa = 3;
-      break;
-    case bfd_mach_mips4K:
-      target_processor = CPU_4K;
-      mips_isa = 2;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips5000:
       target_processor = CPU_R5000;
-      mips_isa = 4;
+      mips_isa = ISA_MIPS4;
       break;
     case bfd_mach_mips6000:
       target_processor = CPU_R6000;
-      mips_isa = 2;
+      mips_isa = ISA_MIPS2;
       break;
     case bfd_mach_mips8000:
       target_processor = CPU_R8000;
-      mips_isa = 4;
+      mips_isa = ISA_MIPS4;
       break;
     case bfd_mach_mips10000:
       target_processor = CPU_R10000;
-      mips_isa = 4;
+      mips_isa = ISA_MIPS4;
       break;
     case bfd_mach_mips16:
       target_processor = CPU_MIPS16;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
+      break;
+    case bfd_mach_mips32:
+      target_processor = CPU_MIPS32;
+      mips_isa = ISA_MIPS32;
+      break;
+    case bfd_mach_mips32_4k:
+      target_processor = CPU_MIPS32_4K;
+      mips_isa = ISA_MIPS32;
       break;
     default:
       target_processor = CPU_R3000;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     }
 

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 3e19ffa..622a231 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -77,8 +77,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define I3     INSN_ISA3
 #define I4     INSN_ISA4
 #define I5     INSN_ISA5
+#define I32    INSN_ISA32
+
 #define P3     INSN_4650
-#define P4     INSN_MIPS32
 #define L1     INSN_4010
 #define V1      INSN_4100
 #define T3      INSN_3900
@@ -113,9 +114,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
 /* name,    args,      match,      mask,       pinfo,          membership */
-{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           G3|M1|P4},
+{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           G3|M1|I32},
 {"nop",     "",         0x00000000, 0xffffffff, 0,              I1      },
-{"ssnop",   "",         0x00000040, 0xffffffff, 0,              M1|P4   },
+{"ssnop",   "",         0x00000040, 0xffffffff, 0,              M1|I32  },
 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,          I1      }, /* addiu */
 {"li",     "t,i",      0x34000000, 0xffe00000, WR_t,           I1      }, /* ori */
 {"li",      "t,I",     0,    (int) M_LI,       INSN_MACRO,     I1      },
@@ -223,7 +224,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bnel",    "s,t,p",   0x54000000, 0xfc000000, CBL|RD_s|RD_t,  I2|T3   },
 {"bnel",    "s,I,p",   0,    (int) M_BNEL_I,   INSN_MACRO,     I2      },
 {"break",   "",                0x0000000d, 0xffffffff, TRAP,           I1      },
-{"break",   "B",        0x0000000d, 0xfc00003f, TRAP,           P4      },
+{"break",   "B",        0x0000000d, 0xfc00003f, TRAP,           I32     },
 {"break",   "c",       0x0000000d, 0xfc00ffff, TRAP,           I1      },
 {"break",   "c,q",     0x0000000d, 0xfc00003f, TRAP,           I1      },
 {"c.f.d",   "S,T",     0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
@@ -322,7 +323,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.ngt.s", "M,S,T",   0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|M1   },
 {"c.ngt.ps","S,T",     0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ngt.ps","M,S,T",   0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
-{"cache",   "k,o(b)",  0xbc000000, 0xfc000000, RD_b,           I3|T3|M1|P4     },
+{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,           I3|T3|M1|I32    },
 {"ceil.l.d", "D,S",    0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3      },
 {"ceil.l.s", "D,S",    0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3      },
 {"ceil.w.d", "D,S",    0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2      },
@@ -332,8 +333,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cfc1",    "t,S",     0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    I1      },
 {"cfc2",    "t,G",     0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1      },
 {"cfc3",    "t,G",     0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1      },
-{"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|RD_s,      P4      },
-{"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|RD_s,      P4      },
+{"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|RD_s,      I32     },
+{"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|RD_s,      I32     },
 {"ctc0",    "t,G",     0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1      },
 {"ctc1",    "t,G",     0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    I1      },
 {"ctc1",    "t,S",     0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    I1      },
@@ -362,7 +363,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* dctr and dctw are used on the r5000.  */
 {"dctr",    "o(b)",    0xbc050000, 0xfc1f0000, RD_b,   I3      },
 {"dctw",    "o(b)",    0xbc090000, 0xfc1f0000, RD_b,   I3      },
-{"deret",   "",         0x4200001f, 0xffffffff,    0,  G2|M1|P4        },
+{"deret",   "",         0x4200001f, 0xffffffff, 0,      G2|M1|I32       },
 /* For ddiv, see the comments about div.  */
 {"ddiv",    "z,s,t",   0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
 {"ddiv",    "d,v,t",   0,    (int) M_DDIV_3,   INSN_MACRO,     I3      },
@@ -434,7 +435,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsub",    "d,v,I",   0,    (int) M_DSUB_I,   INSN_MACRO,     I3      },
 {"dsubu",   "d,v,t",   0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3      },
 {"dsubu",   "d,v,I",   0,    (int) M_DSUBU_I,  INSN_MACRO,     I3      },
-{"eret",    "",                0x42000018, 0xffffffff, 0,      I3|M1|P4        },
+{"eret",    "",         0x42000018, 0xffffffff, 0,              I3|M1|I32},
 {"floor.l.d", "D,S",   0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3      },
 {"floor.l.s", "D,S",   0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3      },
 {"floor.w.d", "D,S",   0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2      },
@@ -531,29 +532,29 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lwu",     "t,o(b)",  0x9c000000, 0xfc000000, LDD|RD_b|WR_t,  I3      },
 {"lwu",     "t,A(b)",  0,    (int) M_LWU_AB,   INSN_MACRO,     I3      },
 {"lwxc1",   "D,t(b)",  0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     I4      },
-{"mad",            "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3|P4   },
-{"madu",    "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3|P4   },
+{"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3|I32  },
+{"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3|I32  },
 {"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
 {"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I5      },
 {"madd",    "s,t",     0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          L1      },
-{"madd",    "s,t",     0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P4      },
+{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      I32     },
 {"madd",    "s,t",     0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M,             G1|M1   },
 {"madd",    "d,s,t",   0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,        G1      },
 {"maddu",   "s,t",     0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          L1      },
-{"maddu",   "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P4      },
+{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      I32     },
 {"maddu",   "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M,     G1|M1},
 {"maddu",   "d,s,t",   0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,        G1},
 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,     V1      },
 {"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1      },
-{"mfc0",    "t,G,H",   0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, P4      },
+{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32     },
 {"mfc1",    "t,S",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I1},
 {"mfc1",    "t,G",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I1},
-{"mfc1",    "t,G,H",    0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S,     P4},
+{"mfc1",    "t,G,H",    0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S,     I32},
 {"mfc2",    "t,G",     0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1      },
-{"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, P4      },
+{"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32     },
 {"mfc3",    "t,G",     0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1      },
-{"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, P4      },
+{"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32     },
 {"mfhi",    "d",       0x00000010, 0xffff07ff, WR_d|RD_HI,     I1      },
 {"mflo",    "d",       0x00000012, 0xffff07ff, WR_d|RD_LO,     I1      },
 {"mov.d",   "D,S",     0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1      },
@@ -563,7 +564,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movf.d",  "D,S,N",   0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|M1   },
 {"movf.s",  "D,S,N",   0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|M1   },
 {"movf.ps", "D,S,N",   0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I5      },
-{"movn",    "d,v,t",   0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|P4        },
+{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|I32       },
 {"ffc",     "d,v",     0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1    },
 {"movn.d",  "D,S,t",   0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|M1   },
 {"movn.s",  "D,S,t",   0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|M1   },
@@ -571,7 +572,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movt.d",  "D,S,N",   0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|M1   },
 {"movt.s",  "D,S,N",   0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|M1   },
 {"movt.ps", "D,S,N",   0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I5},
-{"movz",    "d,v,t",   0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|P4        },
+{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|I32       },
 {"ffs",     "d,v",     0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1    },
 {"movz.d",  "D,S,t",   0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|M1   },
 {"movz.s",  "D,S,t",   0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|M1   },
@@ -580,24 +581,24 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I5      },
 {"msub",    "s,t",     0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1        },
-{"msub",    "s,t",     0x70000004, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P4      },
+{"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      I32     },
 {"msubu",   "s,t",     0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1        },
-{"msubu",   "s,t",     0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P4      },
+{"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      I32     },
 {"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   I1      },
-{"mtc0",    "t,G,H",   0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   P4      },
+{"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I32     },
 {"mtc1",    "t,S",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I1      },
 {"mtc1",    "t,G",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I1      },
-{"mtc1",    "t,G,H",    0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S,     P4      },
+{"mtc1",    "t,G,H",    0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S,     I32     },
 {"mtc2",    "t,G",     0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   I1      },
-{"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   P4      },
+{"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   I32     },
 {"mtc3",    "t,G",     0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   I1      },
-{"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   P4      },
+{"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   I32     },
 {"mthi",    "s",       0x00000011, 0xfc1fffff, RD_s|WR_HI,     I1      },
 {"mtlo",    "s",       0x00000013, 0xfc1fffff, RD_s|WR_LO,     I1      },
 {"mul.d",   "D,V,T",   0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },
 {"mul.s",   "D,V,T",   0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
 {"mul.ps",  "D,V,T",   0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
-{"mul",     "d,v,t",   0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     P3|P4   },
+{"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     P3|I32  },
 {"mul",     "d,v,t",   0,    (int) M_MUL,      INSN_MACRO,     I1      },
 {"mul",     "d,v,I",   0,    (int) M_MUL_I,    INSN_MACRO,     I1      },
 {"mulo",    "d,v,t",   0,    (int) M_MULO,     INSN_MACRO,     I1      },
@@ -667,7 +668,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdbbp",   "",                0x0000000e, 0xffffffff, TRAP,           G2|M1   },
 {"sdbbp",   "c",       0x0000000e, 0xfc00ffff, TRAP,           G2|M1   },
 {"sdbbp",   "c,q",     0x0000000e, 0xfc00003f, TRAP,           G2|M1   },
-{"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,           P4      },
+{"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,           I32     },
 {"sdc1",    "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
 {"sdc1",    "E,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
 {"sdc1",    "T,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,     I2      },
@@ -775,10 +776,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tgeu",    "s,t,q",   0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2       },
 {"tgeu",    "s,j",     0x04090000, 0xfc1f0000, RD_s|TRAP,      I2              }, /* tgeiu */
 {"tgeu",    "s,I",     0,    (int) M_TGEU_I,   INSN_MACRO,     I2      },
-{"tlbp",    "",                0x42000008, 0xffffffff, INSN_TLB,       I1|M1|P4        },
-{"tlbr",    "",                0x42000001, 0xffffffff, INSN_TLB,       I1|M1|P4        },
-{"tlbwi",   "",                0x42000002, 0xffffffff, INSN_TLB,       I1|M1|P4        },
-{"tlbwr",   "",                0x42000006, 0xffffffff, INSN_TLB,       I1|M1|P4        },
+{"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,       I1|M1|I32       },
+{"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,       I1|M1|I32       },
+{"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,       I1|M1|I32       },
+{"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,       I1|M1|I32       },
 {"tlti",    "s,j",     0x040a0000, 0xfc1f0000, RD_s|TRAP,      I2              },
 {"tlt",     "s,t",     0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2       },
 {"tlt",     "s,t,q",   0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2       },
@@ -819,8 +820,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"xor",     "d,v,t",   0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1      },
 {"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,     I1      },
 {"xori",    "t,r,i",   0x38000000, 0xfc000000, WR_t|RD_s,      I1      },
-{"wait",    "",                0x42000020, 0xffffffff, TRAP,   I3|M1|P4        },
-{"wait",    "J",        0x42000020, 0xfe00003f, TRAP,   P4      },
+{"wait",    "",         0x42000020, 0xffffffff, TRAP,   I3|M1|I32       },
+{"wait",    "J",        0x42000020, 0xfe00003f, TRAP,   I32     },
 {"waiti",   "",                0x42000020, 0xffffffff, TRAP,   L1      },
 {"wb",             "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,        L1      },
 /* No hazard protection on coprocessor instructions--they shouldn't

diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot
index ab99ee1..f65a42b 100644 (file)
--- a/opcodes/po/opcodes.pot
+++ b/opcodes/po/opcodes.pot
@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2000-09-05 17:03-0700\n"
+"POT-Creation-Date: 2000-12-01 13:18-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -22,7 +22,8 @@ msgstr ""
 msgid "jump hint unaligned"
 msgstr ""
 
-#: arc-dis.c:232
+#. Default text to print if an instruction isn't recognized.
+#: arc-dis.c:232 fr30-dis.c:39 m32r-dis.c:39
 msgid "*unknown*"
 msgstr ""
 
@@ -48,21 +49,21 @@ msgstr ""
 msgid "branch address not on 4 byte boundary"
 msgstr ""
 
-#: arm-dis.c:466
+#: arm-dis.c:489
 msgid "<illegal precision>"
 msgstr ""
 
-#: arm-dis.c:878
+#: arm-dis.c:904
 #, c-format
 msgid "Unrecognised register name set: %s\n"
 msgstr ""
 
-#: arm-dis.c:885
+#: arm-dis.c:911
 #, c-format
 msgid "Unrecognised disassembler option: %s\n"
 msgstr ""
 
-#: arm-dis.c:1049
+#: arm-dis.c:1075
 msgid ""
 "\n"
 "The following ARM specific disassembler options are supported for use with\n"
@@ -203,6 +204,10 @@ msgstr ""
 msgid "%02x\t\t*unknown*"
 msgstr ""
 
+#: i386-dis.c:1949
+msgid "<internal disassembler error>"
+msgstr ""
+
 #: m10200-dis.c:199
 #, c-format
 msgid "unknown\t0x%02x"
@@ -233,7 +238,7 @@ msgstr ""
 msgid "# <dis error: %08x>"
 msgstr ""
 
-#: mips-dis.c:242
+#: mips-dis.c:273
 #, c-format
 msgid "# internal error, undefined modifier(%c)"
 msgstr ""
@@ -277,21 +282,21 @@ msgid "invalid register operand when updating"
 msgstr ""
 
 #. Mark as non-valid instruction
-#: sparc-dis.c:743
+#: sparc-dis.c:748
 msgid "unknown"
 msgstr ""
 
-#: sparc-dis.c:815
+#: sparc-dis.c:823
 #, c-format
 msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr ""
 
-#: sparc-dis.c:826
+#: sparc-dis.c:834
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr ""
 
-#: sparc-dis.c:875
+#: sparc-dis.c:883
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
 msgstr ""