Phy: DT binding documentation for Marvell MVEBU SATA phy.

Describe the binding for the Marvell MVEBU SATA phy. This driver
can be used at least with Kirkwood, Dove and maybe others.
Additionally, update the SATA binding with the properties to link
to the phy nodes.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt
index 1c83516..b460edd 100644 (file)
--- a/Documentation/devicetree/bindings/ata/marvell.txt
+++ b/Documentation/devicetree/bindings/ata/marvell.txt
@@ -6,11 +6,17 @@ Required Properties:
 - interrupts    : Interrupt controller is using
 - nr-ports      : Number of SATA ports in use.
 
+Optional Properties:
+- phys         : List of phandles to sata phys
+- phy-names    : Should be "0", "1", etc, one number per phandle
+
 Example:
 
        sata@80000 {
                compatible = "marvell,orion-sata";
                reg = <0x80000 0x5000>;
                interrupts = <21>;
+               phys = <&sata_phy0>, <&sata_phy1>;
+               phy-names = "0", "1";
                nr-ports = <2>;
        }

diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu.txt b/Documentation/devicetree/bindings/phy/phy-mvebu.txt
new file mode 100644 (file)
index 0000000..6cb3364
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu.txt
@@ -0,0 +1,22 @@
+* Marvell MVEBU SATA PHY
+
+Power control for the SATA phy found on Marvell MVEBU SoCs.
+
+This document extends the binding described in phy-bindings.txt
+
+Required properties :
+
+ - reg            : Offset and length of the register set for the SATA device
+ - compatible     : Should be "marvell,mvebu-sata-phy"
+ - clocks         : phandle of clock and specifier that supplies the device
+ - clock-names    : Should be "sata"
+
+Example:
+               sata-phy@84000 {
+                       compatible = "marvell,mvebu-sata-phy";
+                       reg = <0x84000 0x0334>;
+                       clocks = <&gate_clk 15>;
+                       clock-names = "sata";
+                       #phy-cells = <0>;
+                       status = "ok";
+               };