#define I2C_CTRL_STATUS 0x00 /* Device Interrupt Status */
#define I2C_CTRL_ASSIGN 0x08 /* Device Interrupt Target
Assignment */
+#define I2C_CTRL_GLOBAL 0x0C /* Global Control Register */
+#define I2C_CTRL_SRAM_EN BIT(0)
/* I2C Device (Bus) Register */
}
}
+static bool aspeed_i2c_check_sram(AspeedI2CBus *bus)
+{
+ AspeedI2CState *s = bus->controller;
+ AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);
+
+ if (!aic->check_sram) {
+ return true;
+ }
+
+ /*
+ * AST2500: SRAM must be enabled before using the Buffer Pool or
+ * DMA mode.
+ */
+ if (!(s->ctrl_global & I2C_CTRL_SRAM_EN) &&
+ (bus->cmd & (I2CD_RX_DMA_ENABLE | I2CD_TX_DMA_ENABLE |
+ I2CD_RX_BUFF_ENABLE | I2CD_TX_BUFF_ENABLE))) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SRAM is not enabled\n", __func__);
+ return false;
+ }
+
+ return true;
+}
+
/*
* The state machine needs some refinement. It is only used to track
* invalid STOP commands for the moment.
bus->cmd &= ~0xFFFF;
bus->cmd |= value & 0xFFFF;
+ if (!aspeed_i2c_check_sram(bus)) {
+ return;
+ }
+
if (bus->cmd & I2CD_M_START_CMD) {
uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?
I2CD_MSTARTR : I2CD_MSTART;
switch (offset) {
case I2C_CTRL_STATUS:
return s->intr_status;
+ case I2C_CTRL_GLOBAL:
+ return s->ctrl_global;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
+ AspeedI2CState *s = opaque;
+
switch (offset) {
+ case I2C_CTRL_GLOBAL:
+ s->ctrl_global = value;
+ break;
case I2C_CTRL_STATUS:
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
aic->pool_size = 0x100;
aic->pool_base = 0x200;
aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base;
+ aic->check_sram = true;
}
static const TypeInfo aspeed_2500_i2c_info = {