instruction register added.

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index fbba807..a783359 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -1,7 +1,10 @@
 library ieee;
 use ieee.std_logic_1164.all;
-use std.textio.all;
 use ieee.std_logic_arith.conv_std_logic_vector;
+use ieee.std_logic_unsigned.all;
+
+---for debug....
+use std.textio.all;
 
 entity mos6502 is 
     generic (   dsize : integer := 8;
@@ -51,6 +54,7 @@ begin
     phi2 <= not input_clk;
     set_clk <= input_clk;
     trigger_clk <= not input_clk;
+    instruction <= d_io;
 
     --addr(asize - 1 downto dsize) <= internal_abus_h;
     --addr(dsize - 1 downto 0) <= internal_abus_l;
@@ -61,6 +65,7 @@ begin
             cur_status <= reset0;
             pc <= conv_std_logic_vector(16#8000#, asize);
         end if;
+
         if (set_clk'event and set_clk = '1') then
             ---one byte instruction decoding.
             if instruction = conv_std_logic_vector(16#78#, dsize) then
@@ -88,6 +93,7 @@ begin
                     addr <= pc;
                 when sei => 
                     cur_status <= fetch;
+                    pc <= pc + 1;
                     d_print(string'("sei 0"));
                 when others => 
                     null;