../m6502_base.cpp
../mb8877.cpp
-# ../mc6800.cpp
+ ../mc6800.cpp
+ ../mc6801.cpp
+ ../hd6301.cpp
+ ../mb8861.cpp
# MC6809 is temporally.
../mc6809_base.cpp
../mc6820.cpp
# ${SDL2_LIBRARIES}
# )
#set_target_properties(CSPcommon_vm PROPERTIES
-# SOVERSION 1.1.11
-# VERSION 1.1.11
+# SOVERSION 1.1.14
+# VERSION 1.1.14
# LINK_INTERFACE_LIBRARIES ""
# )
#generate_export_header(CSPcommon_vm
${s_vm_common_vm_srcs}
)
set_target_properties(CSPcommon_vm PROPERTIES
- SOVERSION 1.1.13
- VERSION 1.1.13
+ SOVERSION 1.1.14
+ VERSION 1.1.14
)
INSTALL(TARGETS CSPcommon_vm DESTINATION ${LIBCSP_INSTALL_DIR})
endif()
#include "../beep.h"
#include "../hd146818p.h"
#include "../i8255.h"
-#include "../mc6800.h"
+//#include "../mc6800.h"
+#include "../hd6301.h"
#include "../noise.h"
#include "../tf20.h"
#include "../upd765a.h"
beep = new BEEP(this, emu);
rtc = new HD146818P(this, emu);
- cpu = new MC6800(this, emu);
+ //cpu = new MC6800(this, emu);
+ cpu = new HD6301(this, emu);
tf20 = new TF20(this, emu);
pio_tf20 = new I8255(this, emu);
fdc_tf20 = new UPD765A(this, emu);
class BEEP;
class HD146818P;
class I8255;
-class MC6800;
+//class MC6800;
+class HD6301;
class TF20;
class UPD765A;
class Z80;
BEEP* beep;
HD146818P* rtc;
- MC6800* cpu;
+ //MC6800* cpu;
+ HD6301* cpu;
TF20* tf20;
I8255* pio_tf20;
#include "memory.h"
#include "../beep.h"
-#include "../mc6800.h"
+#include "../hd6301.h"
#include "../z80sio.h"
#include "../../fifo.h"
--- /dev/null
+
+/*
+ Skelton for retropc emulator
+
+ Origin : MAME 0.142
+ Author : Takeda.Toshiya
+ Date : 2011.04.23-
+
+ [ MC6801 ]
+*/
+#if defined(_MSC_VER) && (_MSC_VER >= 1400)
+#pragma warning( disable : 4996 )
+#endif
+
+#include "hd6301.h"
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+#include "../fifo.h"
+//#endif
+//#ifdef USE_DEBUGGER
+#include "debugger.h"
+#include "mc6800_consts.h"
+#include "mc6801_consts.h"
+//#endif
+
+void HD6301::mc6801_io_w(uint32_t offset, uint32_t data)
+{
+ switch(offset) {
+ case 0x00:
+ // port1 data direction register
+ port[0].ddr = data;
+ break;
+ case 0x01:
+ // port2 data direction register
+ port[1].ddr = data;
+ break;
+ case 0x02:
+ // port1 data register
+ if(port[0].wreg != data || port[0].first_write) {
+ write_signals(&port[0].outputs, data);
+ port[0].wreg = data;
+ port[0].first_write = false;
+ }
+ break;
+ case 0x03:
+ // port2 data register
+ if(port[1].wreg != data || port[1].first_write) {
+ write_signals(&port[1].outputs, data);
+ port[1].wreg = data;
+ port[1].first_write = false;
+ }
+ break;
+ case 0x04:
+ // port3 data direction register
+ port[2].ddr = data;
+ break;
+ case 0x05:
+ // port4 data direction register
+ port[3].ddr = data;
+ break;
+ case 0x06:
+ // port3 data register
+ if(p3csr_is3_flag_read) {
+ p3csr_is3_flag_read = false;
+ p3csr &= ~P3CSR_IS3_FLAG;
+ }
+ if(port[2].wreg != data || port[2].first_write) {
+ write_signals(&port[2].outputs, data);
+ port[2].wreg = data;
+ port[2].first_write = false;
+ }
+ break;
+ case 0x07:
+ // port4 data register
+ if(port[3].wreg != data || port[3].first_write) {
+ write_signals(&port[3].outputs, data);
+ port[3].wreg = data;
+ port[3].first_write = false;
+ }
+ break;
+ case 0x08:
+ // timer control/status register
+ tcsr = data;
+ pending_tcsr &= tcsr;
+ break;
+ case 0x09:
+ // free running counter (msb)
+//#ifdef HAS_HD6301
+ latch09 = data & 0xff;
+//#endif
+ CT = 0xfff8;
+ TOH = CTH;
+ MODIFIED_counters;
+ break;
+//#ifdef HAS_HD6301
+ case 0x0a:
+ // free running counter (lsb)
+ CT = (latch09 << 8) | (data & 0xff);
+ TOH = CTH;
+ MODIFIED_counters;
+ break;
+//#endif
+ case 0x0b:
+ // output compare register (msb)
+ if(output_compare.b.h != data) {
+ output_compare.b.h = data;
+ MODIFIED_counters;
+ }
+ tcsr &=~TCSR_OCF;
+ break;
+ case 0x0c:
+ // output compare register (lsb)
+ if(output_compare.b.l != data) {
+ output_compare.b.l = data;
+ MODIFIED_counters;
+ }
+ tcsr &=~TCSR_OCF;
+ break;
+ case 0x0f:
+ // port3 control/status register
+ p3csr = (p3csr & P3CSR_IS3_FLAG) | (data & ~P3CSR_IS3_FLAG);
+ break;
+ case 0x10:
+ // rate and mode control register
+ rmcr = data;
+ break;
+ case 0x11:
+ // transmit/receive control/status register
+ trcsr = (trcsr & 0xe0) | (data & 0x1f);
+ break;
+ case 0x13:
+ // transmit data register
+ if(trcsr_read_tdre) {
+ trcsr_read_tdre = false;
+ trcsr &= ~TRCSR_TDRE;
+ }
+ tdr = data;
+ break;
+ case 0x14:
+ // ram control register
+ ram_ctrl = data;
+ break;
+ }
+}
+
+void HD6301::insn(uint8_t code)
+{
+ switch(code) {
+ case 0x00: illegal(); break;
+ case 0x01: nop(); break;
+ case 0x02: illegal(); break;
+ case 0x03: illegal(); break;
+ case 0x04: lsrd(); break;
+ case 0x05: asld(); break;
+ case 0x06: tap(); break;
+ case 0x07: tpa(); break;
+ case 0x08: inx(); break;
+ case 0x09: dex(); break;
+ case 0x0a: clv(); break;
+ case 0x0b: sev(); break;
+ case 0x0c: clc(); break;
+ case 0x0d: sec(); break;
+ case 0x0e: cli(); break;
+ case 0x0f: sei(); break;
+ case 0x10: sba(); break;
+ case 0x11: cba(); break;
+
+ case 0x12: undoc1(); break;
+ case 0x13: undoc2(); break;
+
+ case 0x14: illegal(); break;
+ case 0x15: illegal(); break;
+ case 0x16: tab(); break;
+ case 0x17: tba(); break;
+
+ case 0x18: xgdx(); break;
+
+ case 0x19: daa(); break;
+
+ case 0x1a: slp(); break;
+
+ case 0x1b: aba(); break;
+ case 0x1c: illegal(); break;
+ case 0x1d: illegal(); break;
+ case 0x1e: illegal(); break;
+ case 0x1f: illegal(); break;
+ case 0x20: bra(); break;
+ case 0x21: brn(); break;
+ case 0x22: bhi(); break;
+ case 0x23: bls(); break;
+ case 0x24: bcc(); break;
+ case 0x25: bcs(); break;
+ case 0x26: bne(); break;
+ case 0x27: beq(); break;
+ case 0x28: bvc(); break;
+ case 0x29: bvs(); break;
+ case 0x2a: bpl(); break;
+ case 0x2b: bmi(); break;
+ case 0x2c: bge(); break;
+ case 0x2d: blt(); break;
+ case 0x2e: bgt(); break;
+ case 0x2f: ble(); break;
+ case 0x30: tsx(); break;
+ case 0x31: ins(); break;
+ case 0x32: pula(); break;
+ case 0x33: pulb(); break;
+ case 0x34: des(); break;
+ case 0x35: txs(); break;
+ case 0x36: psha(); break;
+ case 0x37: pshb(); break;
+
+ case 0x38: pulx(); break;
+
+ case 0x39: rts(); break;
+
+ case 0x3a: abx(); break;
+
+ case 0x3b: rti(); break;
+
+ case 0x3c: pshx(); break;
+ case 0x3d: mul(); break;
+
+ case 0x3e: wai(); break;
+ case 0x3f: swi(); break;
+ case 0x40: nega(); break;
+ case 0x41: illegal(); break;
+ case 0x42: illegal(); break;
+ case 0x43: coma(); break;
+ case 0x44: lsra(); break;
+ case 0x45: illegal(); break;
+ case 0x46: rora(); break;
+ case 0x47: asra(); break;
+ case 0x48: asla(); break;
+ case 0x49: rola(); break;
+ case 0x4a: deca(); break;
+ case 0x4b: illegal(); break;
+ case 0x4c: inca(); break;
+ case 0x4d: tsta(); break;
+ case 0x4e: illegal(); break;
+ case 0x4f: clra(); break;
+ case 0x50: negb(); break;
+ case 0x51: illegal(); break;
+ case 0x52: illegal(); break;
+ case 0x53: comb(); break;
+ case 0x54: lsrb(); break;
+ case 0x55: illegal(); break;
+ case 0x56: rorb(); break;
+ case 0x57: asrb(); break;
+ case 0x58: aslb(); break;
+ case 0x59: rolb(); break;
+ case 0x5a: decb(); break;
+ case 0x5b: illegal(); break;
+ case 0x5c: incb(); break;
+ case 0x5d: tstb(); break;
+ case 0x5e: illegal(); break;
+ case 0x5f: clrb(); break;
+ case 0x60: neg_ix(); break;
+
+ case 0x61: aim_ix(); break;
+ case 0x62: oim_ix(); break;
+
+ case 0x63: com_ix(); break;
+ case 0x64: lsr_ix(); break;
+
+ case 0x65: eim_ix(); break;
+
+ case 0x66: ror_ix(); break;
+ case 0x67: asr_ix(); break;
+ case 0x68: asl_ix(); break;
+ case 0x69: rol_ix(); break;
+ case 0x6a: dec_ix(); break;
+
+ case 0x6b: tim_ix(); break;
+
+ case 0x6c: inc_ix(); break;
+ case 0x6d: tst_ix(); break;
+ case 0x6e: jmp_ix(); break;
+ case 0x6f: clr_ix(); break;
+ case 0x70: neg_ex(); break;
+
+ case 0x71: aim_di(); break;
+ case 0x72: oim_di(); break;
+
+ case 0x73: com_ex(); break;
+ case 0x74: lsr_ex(); break;
+
+ case 0x75: eim_di(); break;
+
+ case 0x76: ror_ex(); break;
+ case 0x77: asr_ex(); break;
+ case 0x78: asl_ex(); break;
+ case 0x79: rol_ex(); break;
+ case 0x7a: dec_ex(); break;
+
+ case 0x7b: tim_di(); break;
+
+ case 0x7c: inc_ex(); break;
+ case 0x7d: tst_ex(); break;
+ case 0x7e: jmp_ex(); break;
+ case 0x7f: clr_ex(); break;
+ case 0x80: suba_im(); break;
+ case 0x81: cmpa_im(); break;
+ case 0x82: sbca_im(); break;
+
+ case 0x83: subd_im(); break;
+
+ case 0x84: anda_im(); break;
+ case 0x85: bita_im(); break;
+ case 0x86: lda_im(); break;
+ case 0x87: sta_im(); break;
+ case 0x88: eora_im(); break;
+ case 0x89: adca_im(); break;
+ case 0x8a: ora_im(); break;
+ case 0x8b: adda_im(); break;
+
+ case 0x8c: cpx_im (); break;
+ case 0x8d: bsr(); break;
+ case 0x8e: lds_im(); break;
+ case 0x8f: sts_im(); break;
+ case 0x90: suba_di(); break;
+ case 0x91: cmpa_di(); break;
+ case 0x92: sbca_di(); break;
+
+ case 0x93: subd_di(); break;
+
+ case 0x94: anda_di(); break;
+ case 0x95: bita_di(); break;
+ case 0x96: lda_di(); break;
+ case 0x97: sta_di(); break;
+ case 0x98: eora_di(); break;
+ case 0x99: adca_di(); break;
+ case 0x9a: ora_di(); break;
+ case 0x9b: adda_di(); break;
+
+ case 0x9c: cpx_di (); break;
+ case 0x9d: jsr_di(); break;
+ case 0x9e: lds_di(); break;
+ case 0x9f: sts_di(); break;
+ case 0xa0: suba_ix(); break;
+ case 0xa1: cmpa_ix(); break;
+ case 0xa2: sbca_ix(); break;
+
+ case 0xa3: subd_ix(); break;
+ case 0xa4: anda_ix(); break;
+ case 0xa5: bita_ix(); break;
+ case 0xa6: lda_ix(); break;
+ case 0xa7: sta_ix(); break;
+ case 0xa8: eora_ix(); break;
+ case 0xa9: adca_ix(); break;
+ case 0xaa: ora_ix(); break;
+ case 0xab: adda_ix(); break;
+
+ case 0xac: cpx_ix (); break;
+
+ case 0xad: jsr_ix(); break;
+ case 0xae: lds_ix(); break;
+ case 0xaf: sts_ix(); break;
+ case 0xb0: suba_ex(); break;
+ case 0xb1: cmpa_ex(); break;
+ case 0xb2: sbca_ex(); break;
+
+ case 0xb3: subd_ex(); break;
+ case 0xb4: anda_ex(); break;
+ case 0xb5: bita_ex(); break;
+ case 0xb6: lda_ex(); break;
+ case 0xb7: sta_ex(); break;
+ case 0xb8: eora_ex(); break;
+ case 0xb9: adca_ex(); break;
+ case 0xba: ora_ex(); break;
+ case 0xbb: adda_ex(); break;
+
+ case 0xbc: cpx_ex (); break;
+ case 0xbd: jsr_ex(); break;
+ case 0xbe: lds_ex(); break;
+ case 0xbf: sts_ex(); break;
+ case 0xc0: subb_im(); break;
+ case 0xc1: cmpb_im(); break;
+ case 0xc2: sbcb_im(); break;
+
+ case 0xc3: addd_im(); break;
+
+ case 0xc4: andb_im(); break;
+ case 0xc5: bitb_im(); break;
+ case 0xc6: ldb_im(); break;
+ case 0xc7: stb_im(); break;
+ case 0xc8: eorb_im(); break;
+ case 0xc9: adcb_im(); break;
+ case 0xca: orb_im(); break;
+ case 0xcb: addb_im(); break;
+
+ case 0xcc: ldd_im(); break;
+ case 0xcd: std_im(); break;
+
+
+ case 0xce: ldx_im(); break;
+ case 0xcf: stx_im(); break;
+ case 0xd0: subb_di(); break;
+ case 0xd1: cmpb_di(); break;
+ case 0xd2: sbcb_di(); break;
+
+ case 0xd3: addd_di(); break;
+
+ case 0xd4: andb_di(); break;
+ case 0xd5: bitb_di(); break;
+ case 0xd6: ldb_di(); break;
+ case 0xd7: stb_di(); break;
+ case 0xd8: eorb_di(); break;
+ case 0xd9: adcb_di(); break;
+ case 0xda: orb_di(); break;
+ case 0xdb: addb_di(); break;
+
+ case 0xdc: ldd_di(); break;
+ case 0xdd: std_di(); break;
+
+ case 0xde: ldx_di(); break;
+ case 0xdf: stx_di(); break;
+ case 0xe0: subb_ix(); break;
+ case 0xe1: cmpb_ix(); break;
+ case 0xe2: sbcb_ix(); break;
+
+ case 0xe3: addd_ix(); break;
+
+ case 0xe4: andb_ix(); break;
+ case 0xe5: bitb_ix(); break;
+ case 0xe6: ldb_ix(); break;
+ case 0xe7: stb_ix(); break;
+ case 0xe8: eorb_ix(); break;
+ case 0xe9: adcb_ix(); break;
+ case 0xea: orb_ix(); break;
+ case 0xeb: addb_ix(); break;
+
+ case 0xec: ldd_ix(); break;
+ case 0xed: std_ix(); break;
+
+ case 0xee: ldx_ix(); break;
+ case 0xef: stx_ix(); break;
+ case 0xf0: subb_ex(); break;
+ case 0xf1: cmpb_ex(); break;
+ case 0xf2: sbcb_ex(); break;
+
+ case 0xf3: addd_ex(); break;
+
+ case 0xf4: andb_ex(); break;
+ case 0xf5: bitb_ex(); break;
+ case 0xf6: ldb_ex(); break;
+ case 0xf7: stb_ex(); break;
+ case 0xf8: eorb_ex(); break;
+ case 0xf9: adcb_ex(); break;
+ case 0xfa: orb_ex(); break;
+ case 0xfb: addb_ex(); break;
+
+ case 0xfc: ldd_ex(); break;
+ case 0xfd: std_ex(); break;
+
+ case 0xfe: ldx_ex(); break;
+ case 0xff: stx_ex(); break;
+#if defined(_MSC_VER) && (_MSC_VER >= 1200)
+ default: __assume(0);
+#endif
+ }
+}
+
+/* $00 ILLEGAL */
+void HD6301::illegal()
+{
+//#ifdef HAS_HD6301
+ TAKE_TRAP;
+//#endif
+}
+
+/* $12 ILLEGAL */
+void HD6301::undoc1()
+{
+ X += RM(S + 1);
+}
+
+/* $13 ILLEGAL */
+void HD6301::undoc2()
+{
+ X += RM(S + 1);
+}
+
+/* $18 XGDX inherent ----- */ /* HD6301 only */
+void HD6301::xgdx()
+{
+ uint16_t t = X;
+ X = D;
+ D = t;
+}
+
+/* $1a SLP */ /* HD6301 only */
+void HD6301::slp()
+{
+ /* wait for next IRQ (same as waiting of wai) */
+ wai_state |= HD6301_SLP;
+}
+/* $61 AIM --**0- */ /* HD6301 only */
+void HD6301::aim_ix()
+{
+ uint8_t t, r;
+ IMMBYTE(t);
+ IDXBYTE(r);
+ r &= t;
+ CLR_NZV;
+ SET_NZ8(r);
+ WM(EAD, r);
+}
+
+/* $62 OIM --**0- */ /* HD6301 only */
+void HD6301::oim_ix()
+{
+ uint8_t t, r;
+ IMMBYTE(t);
+ IDXBYTE(r);
+ r |= t;
+ CLR_NZV;
+ SET_NZ8(r);
+ WM(EAD, r);
+}
+/* $65 EIM --**0- */ /* HD6301 only */
+void HD6301::eim_ix()
+{
+ uint8_t t, r;
+ IMMBYTE(t);
+ IDXBYTE(r);
+ r ^= t;
+ CLR_NZV;
+ SET_NZ8(r);
+ WM(EAD, r);
+}
+/* $6b TIM --**0- */ /* HD6301 only */
+void HD6301::tim_ix()
+{
+ uint8_t t, r;
+ IMMBYTE(t);
+ IDXBYTE(r);
+ r &= t;
+ CLR_NZV;
+ SET_NZ8(r);
+}
+
+/* $71 AIM --**0- */ /* HD6301 only */
+void HD6301::aim_di()
+{
+ uint8_t t, r;
+ IMMBYTE(t);
+ DIRBYTE(r);
+ r &= t;
+ CLR_NZV;
+ SET_NZ8(r);
+ WM(EAD, r);
+}
+/* $72 OIM --**0- */ /* HD6301 only */
+void HD6301::oim_di()
+{
+ uint8_t t, r;
+ IMMBYTE(t);
+ DIRBYTE(r);
+ r |= t;
+ CLR_NZV;
+ SET_NZ8(r);
+ WM(EAD, r);
+}
+/* $75 EIM --**0- */ /* HD6301 only */
+void HD6301::eim_di()
+{
+ uint8_t t, r;
+ IMMBYTE(t);
+ DIRBYTE(r);
+ r ^= t;
+ CLR_NZV;
+ SET_NZ8(r);
+ WM(EAD, r);
+}
+
+/* $7b TIM --**0- */ /* HD6301 only */
+void HD6301::tim_di()
+{
+ uint8_t t, r;
+ IMMBYTE(t);
+ DIRBYTE(r);
+ r &= t;
+ CLR_NZV;
+ SET_NZ8(r);
+}
+
+int HD6301::debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len)
+{
+ uint8_t ops[4];
+ for(int i = 0; i < 4; i++) {
+ int wait;
+ ops[i] = d_mem_stored->read_data8w(pc + i, &wait);
+ }
+ return Dasm680x(6301, buffer, pc, ops, ops, d_debugger->first_symbol);
+ return 0;
+}
+
+#define STATE_VERSION 1
+
+void HD6301::save_state(FILEIO* state_fio)
+{
+ state_fio->FputUint32(STATE_VERSION);
+ state_fio->FputInt32(this_device_id);
+
+ state_fio->FputUint32(pc.d);
+ state_fio->FputUint16(prevpc);
+ state_fio->FputUint32(sp.d);
+ state_fio->FputUint32(ix.d);
+ state_fio->FputUint32(acc_d.d);
+ state_fio->FputUint32(ea.d);
+ state_fio->FputUint8(cc);
+ state_fio->FputInt32(wai_state);
+ state_fio->FputInt32(int_state);
+ state_fio->FputInt32(icount);
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ for(int i = 0; i < 4; i++) {
+ state_fio->FputUint8(port[i].wreg);
+ state_fio->FputUint8(port[i].rreg);
+ state_fio->FputUint8(port[i].ddr);
+ state_fio->FputUint8(port[i].latched_data);
+ state_fio->FputBool(port[i].latched);
+ state_fio->FputBool(port[i].first_write);
+ }
+ state_fio->FputUint8(p3csr);
+ state_fio->FputBool(p3csr_is3_flag_read);
+ state_fio->FputBool(sc1_state);
+ state_fio->FputBool(sc2_state);
+ state_fio->FputUint32(counter.d);
+ state_fio->FputUint32(output_compare.d);
+ state_fio->FputUint32(timer_over.d);
+ state_fio->FputUint8(tcsr);
+ state_fio->FputUint8(pending_tcsr);
+ state_fio->FputUint16(input_capture);
+//#ifdef HAS_HD6301
+ state_fio->FputUint16(latch09);
+//#endif
+ state_fio->FputUint32(timer_next);
+ recv_buffer->save_state((void *)state_fio);
+ state_fio->FputUint8(trcsr);
+ state_fio->FputUint8(rdr);
+ state_fio->FputUint8(tdr);
+ state_fio->FputBool(trcsr_read_tdre);
+ state_fio->FputBool(trcsr_read_orfe);
+ state_fio->FputBool(trcsr_read_rdrf);
+ state_fio->FputUint8(rmcr);
+ state_fio->FputInt32(sio_counter);
+ state_fio->FputUint8(ram_ctrl);
+ state_fio->Fwrite(ram, sizeof(ram), 1);
+//#endif
+}
+
+bool HD6301::load_state(FILEIO* state_fio)
+{
+ if(state_fio->FgetUint32() != STATE_VERSION) {
+ return false;
+ }
+ if(state_fio->FgetInt32() != this_device_id) {
+ return false;
+ }
+ pc.d = state_fio->FgetUint32();
+ prevpc = state_fio->FgetUint16();
+ sp.d = state_fio->FgetUint32();
+ ix.d = state_fio->FgetUint32();
+ acc_d.d = state_fio->FgetUint32();
+ ea.d = state_fio->FgetUint32();
+ cc = state_fio->FgetUint8();
+ wai_state = state_fio->FgetInt32();
+ int_state = state_fio->FgetInt32();
+ icount = state_fio->FgetInt32();
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ for(int i = 0; i < 4; i++) {
+ port[i].wreg = state_fio->FgetUint8();
+ port[i].rreg = state_fio->FgetUint8();
+ port[i].ddr = state_fio->FgetUint8();
+ port[i].latched_data = state_fio->FgetUint8();
+ port[i].latched = state_fio->FgetBool();
+ port[i].first_write = state_fio->FgetBool();
+ }
+ p3csr = state_fio->FgetUint8();
+ p3csr_is3_flag_read = state_fio->FgetBool();
+ sc1_state = state_fio->FgetBool();
+ sc2_state = state_fio->FgetBool();
+ counter.d = state_fio->FgetUint32();
+ output_compare.d = state_fio->FgetUint32();
+ timer_over.d = state_fio->FgetUint32();
+ tcsr = state_fio->FgetUint8();
+ pending_tcsr = state_fio->FgetUint8();
+ input_capture = state_fio->FgetUint16();
+//#ifdef HAS_HD6301
+ latch09 = state_fio->FgetUint16();
+//#endif
+ timer_next = state_fio->FgetUint32();
+ if(!recv_buffer->load_state((void *)state_fio)) {
+ return false;
+ }
+ trcsr = state_fio->FgetUint8();
+ rdr = state_fio->FgetUint8();
+ tdr = state_fio->FgetUint8();
+ trcsr_read_tdre = state_fio->FgetBool();
+ trcsr_read_orfe = state_fio->FgetBool();
+ trcsr_read_rdrf = state_fio->FgetBool();
+ rmcr = state_fio->FgetUint8();
+ sio_counter = state_fio->FgetInt32();
+ ram_ctrl = state_fio->FgetUint8();
+ state_fio->Fread(ram, sizeof(ram), 1);
+//#endif
+ return true;
+}
--- /dev/null
+#ifndef _HD6301_H_
+#define _HD6301_H_
+
+#include "mc6801.h"
+#include "device.h"
+
+class DEBUGGER;
+class FIFO;
+//#endif
+class HD6301 : public MC6801
+{
+protected:
+#define XX 5
+ const uint8_t cycles[256] = {
+//#elif defined(HAS_HD6301)
+ XX, 1,XX,XX, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1,XX,XX,XX,XX, 1, 1, 2, 2, 4, 1,XX,XX,XX,XX,
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 1, 1, 3, 3, 1, 1, 4, 4, 4, 5, 1,10, 5, 7, 9,12,
+ 1,XX,XX, 1, 1,XX, 1, 1, 1, 1, 1,XX, 1, 1,XX, 1,
+ 1,XX,XX, 1, 1,XX, 1, 1, 1, 1, 1,XX, 1, 1,XX, 1,
+ 6, 7, 7, 6, 6, 7, 6, 6, 6, 6, 6, 5, 6, 4, 3, 5,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 4, 6, 4, 3, 5,
+ 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 2, 3, 5, 3, 3,
+ 3, 3, 3, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 5, 4, 4,
+ 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
+ 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 6, 5, 5,
+ 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 2, 3,XX, 3, 3,
+ 3, 3, 3, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4,
+ 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
+ 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5
+//#elif defined(HAS_MB8861)
+ };
+#undef XX
+ uint16_t latch09;
+
+ void mc6801_io_w(uint32_t offset, uint32_t data) override;
+ void insn(uint8_t code) override;
+
+ void undoc1();
+ void undoc2();
+ void xgdx();
+
+ void slp();
+ void aim_ix();
+ void oim_ix();
+ void eim_ix();
+ void tim_ix();
+ void aim_di();
+ void oim_di();
+ void eim_di();
+ void tim_di();
+
+ void illegal() override;
+
+public:
+ HD6301(VM* parent_vm, EMU* parent_emu) : MC6801(parent_vm, parent_emu)
+ {
+ set_device_name(_T("HD6301 MPU"));
+ }
+ ~HD6301() {}
+ void save_state(FILEIO* state_fio) override;
+ bool load_state(FILEIO* state_fio) override;
+
+ int debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len) override;
+
+};
+#endif
#include "../event.h"
#include "../datarec.h"
-#include "../mc6800.h"
+//#include "../mc6800.h"
+#include "../mb8861.h"
#include "../noise.h"
#include "../not.h"
#include "../pcm1bit.h"
drec->set_context_noise_play(new NOISE(this, emu));
drec->set_context_noise_stop(new NOISE(this, emu));
drec->set_context_noise_fast(new NOISE(this, emu));
- cpu = new MC6800(this, emu); // MB8861N
+ //cpu = new MC6800(this, emu); // MB8861N
+ cpu = new MB8861(this, emu); // MB8861N
not_mic = new NOT(this, emu);
not_mic->set_device_name(_T("NOT Gate (Mic)"));
not_ear = new NOT(this, emu);
class EVENT;
class DATAREC;
-class MC6800;
+//class MC6800;
+class MB8861;
class NOT;
class PCM1BIT;
class SY6522;
EVENT* event;
DATAREC* drec;
- MC6800* cpu;
+ //MC6800* cpu;
+ MB8861* cpu;
NOT* not_mic;
NOT* not_ear;
PCM1BIT* pcm;
#include "../datarec.h"
#include "../hd44102.h"
-#include "../mc6800.h"
+//#include "../mc6800.h"
+#include "../hd6301.h"
#include "../memory.h"
#include "../noise.h"
#include "../pcm1bit.h"
for(int i = 0; i < 8; i++) {
lcd[i] = new HD44102(this, emu);
}
- cpu = new MC6800(this, emu);
+// cpu = new MC6800(this, emu);
+ cpu = new HD6301(this, emu);
memory = new MEMORY(this, emu);
pcm = new PCM1BIT(this, emu);
class DATAREC;
class HD44102;
-class MC6800;
+//class MC6800;
+class HD6301;
class MEMORY;
class PCM1BIT;
DATAREC* drec;
HD44102* lcd[8];
- MC6800* cpu;
+ //MC6800* cpu;
+ HD6301* cpu;
MEMORY* memory;
PCM1BIT* pcm;
--- /dev/null
+/*
+ Skelton for retropc emulator
+
+ Origin : MAME 0.142
+ Author : Takeda.Toshiya
+ Date : 2011.04.23-
+
+ [ MB8861 ]
+*/
+#if defined(_MSC_VER) && (_MSC_VER >= 1400)
+#pragma warning( disable : 4996 )
+#endif
+
+#include "mb8861.h"
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+#include "../fifo.h"
+//#endif
+//#ifdef USE_DEBUGGER
+#include "debugger.h"
+#include "mc6800_consts.h"
+
+
+int MB8861::debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len)
+{
+ uint8_t ops[4];
+ if(d_mem_stored != NULL) {
+ for(int i = 0; i < 4; i++) {
+ int wait;
+ ops[i] = d_mem_stored->read_data8w(pc + i, &wait);
+ }
+ }
+ return Dasm680x(6800, buffer, pc, ops, ops, d_debugger->first_symbol); // FIXME
+ return 0;
+}
+
+void MB8861::insn(uint8_t code)
+{
+ switch(code) {
+ case 0x00: illegal(); break;
+ case 0x01: nop(); break;
+ case 0x02: illegal(); break;
+ case 0x03: illegal(); break;
+ case 0x04: illegal(); break;
+ case 0x05: illegal(); break;
+ case 0x06: tap(); break;
+ case 0x07: tpa(); break;
+ case 0x08: inx(); break;
+ case 0x09: dex(); break;
+ case 0x0a: clv(); break;
+ case 0x0b: sev(); break;
+ case 0x0c: clc(); break;
+ case 0x0d: sec(); break;
+ case 0x0e: cli(); break;
+ case 0x0f: sei(); break;
+ case 0x10: sba(); break;
+ case 0x11: cba(); break;
+ case 0x12: illegal(); break;
+ case 0x13: illegal(); break;
+ case 0x14: illegal(); break;
+ case 0x15: illegal(); break;
+ case 0x16: tab(); break;
+ case 0x17: tba(); break;
+ case 0x18: illegal(); break;
+ case 0x19: daa(); break;
+ case 0x1a: illegal(); break;
+ case 0x1b: aba(); break;
+ case 0x1c: illegal(); break;
+ case 0x1d: illegal(); break;
+ case 0x1e: illegal(); break;
+ case 0x1f: illegal(); break;
+ case 0x20: bra(); break;
+ case 0x21: brn(); break;
+ case 0x22: bhi(); break;
+ case 0x23: bls(); break;
+ case 0x24: bcc(); break;
+ case 0x25: bcs(); break;
+ case 0x26: bne(); break;
+ case 0x27: beq(); break;
+ case 0x28: bvc(); break;
+ case 0x29: bvs(); break;
+ case 0x2a: bpl(); break;
+ case 0x2b: bmi(); break;
+ case 0x2c: bge(); break;
+ case 0x2d: blt(); break;
+ case 0x2e: bgt(); break;
+ case 0x2f: ble(); break;
+ case 0x30: tsx(); break;
+ case 0x31: ins(); break;
+ case 0x32: pula(); break;
+ case 0x33: pulb(); break;
+ case 0x34: des(); break;
+ case 0x35: txs(); break;
+ case 0x36: psha(); break;
+ case 0x37: pshb(); break;
+ case 0x38: illegal(); break;
+ case 0x39: rts(); break;
+ case 0x3a: illegal(); break;
+ case 0x3b: rti(); break;
+ case 0x3c: illegal(); break;
+ case 0x3d: illegal(); break;
+ case 0x3e: wai(); break;
+ case 0x3f: swi(); break;
+ case 0x40: nega(); break;
+ case 0x41: illegal(); break;
+ case 0x42: illegal(); break;
+ case 0x43: coma(); break;
+ case 0x44: lsra(); break;
+ case 0x45: illegal(); break;
+ case 0x46: rora(); break;
+ case 0x47: asra(); break;
+ case 0x48: asla(); break;
+ case 0x49: rola(); break;
+ case 0x4a: deca(); break;
+ case 0x4b: illegal(); break;
+ case 0x4c: inca(); break;
+ case 0x4d: tsta(); break;
+ case 0x4e: illegal(); break;
+ case 0x4f: clra(); break;
+ case 0x50: negb(); break;
+ case 0x51: illegal(); break;
+ case 0x52: illegal(); break;
+ case 0x53: comb(); break;
+ case 0x54: lsrb(); break;
+ case 0x55: illegal(); break;
+ case 0x56: rorb(); break;
+ case 0x57: asrb(); break;
+ case 0x58: aslb(); break;
+ case 0x59: rolb(); break;
+ case 0x5a: decb(); break;
+ case 0x5b: illegal(); break;
+ case 0x5c: incb(); break;
+ case 0x5d: tstb(); break;
+ case 0x5e: illegal(); break;
+ case 0x5f: clrb(); break;
+ case 0x60: neg_ix(); break;
+ case 0x61: illegal(); break;
+ case 0x62: illegal(); break;
+ case 0x63: com_ix(); break;
+ case 0x64: lsr_ix(); break;
+ case 0x65: illegal(); break;
+
+ case 0x66: ror_ix(); break;
+ case 0x67: asr_ix(); break;
+ case 0x68: asl_ix(); break;
+ case 0x69: rol_ix(); break;
+ case 0x6a: dec_ix(); break;
+ case 0x6b: illegal(); break;
+
+ case 0x6c: inc_ix(); break;
+ case 0x6d: tst_ix(); break;
+ case 0x6e: jmp_ix(); break;
+ case 0x6f: clr_ix(); break;
+ case 0x70: neg_ex(); break;
+
+ case 0x71: nim_ix(); break;
+ case 0x72: oim_ix_mb8861(); break;
+
+ case 0x73: com_ex(); break;
+ case 0x74: lsr_ex(); break;
+
+ case 0x75: xim_ix(); break;
+
+ case 0x76: ror_ex(); break;
+ case 0x77: asr_ex(); break;
+ case 0x78: asl_ex(); break;
+ case 0x79: rol_ex(); break;
+ case 0x7a: dec_ex(); break;
+
+ case 0x7b: tmm_ix(); break;
+
+ case 0x7c: inc_ex(); break;
+ case 0x7d: tst_ex(); break;
+ case 0x7e: jmp_ex(); break;
+ case 0x7f: clr_ex(); break;
+ case 0x80: suba_im(); break;
+ case 0x81: cmpa_im(); break;
+ case 0x82: sbca_im(); break;
+ case 0x83: illegal(); break;
+ case 0x84: anda_im(); break;
+ case 0x85: bita_im(); break;
+ case 0x86: lda_im(); break;
+ case 0x87: sta_im(); break;
+ case 0x88: eora_im(); break;
+ case 0x89: adca_im(); break;
+ case 0x8a: ora_im(); break;
+ case 0x8b: adda_im(); break;
+ case 0x8c: cmpx_im(); break;
+ case 0x8d: bsr(); break;
+ case 0x8e: lds_im(); break;
+ case 0x8f: sts_im(); break;
+ case 0x90: suba_di(); break;
+ case 0x91: cmpa_di(); break;
+ case 0x92: sbca_di(); break;
+ case 0x93: illegal(); break;
+ case 0x94: anda_di(); break;
+ case 0x95: bita_di(); break;
+ case 0x96: lda_di(); break;
+ case 0x97: sta_di(); break;
+ case 0x98: eora_di(); break;
+ case 0x99: adca_di(); break;
+ case 0x9a: ora_di(); break;
+ case 0x9b: adda_di(); break;
+ case 0x9c: cmpx_di(); break;
+ case 0x9d: jsr_di(); break;
+ case 0x9e: lds_di(); break;
+ case 0x9f: sts_di(); break;
+ case 0xa0: suba_ix(); break;
+ case 0xa1: cmpa_ix(); break;
+ case 0xa2: sbca_ix(); break;
+ case 0xa3: illegal(); break;
+ case 0xa4: anda_ix(); break;
+ case 0xa5: bita_ix(); break;
+ case 0xa6: lda_ix(); break;
+ case 0xa7: sta_ix(); break;
+ case 0xa8: eora_ix(); break;
+ case 0xa9: adca_ix(); break;
+ case 0xaa: ora_ix(); break;
+ case 0xab: adda_ix(); break;
+ case 0xac: cmpx_ix(); break;
+ case 0xad: jsr_ix(); break;
+ case 0xae: lds_ix(); break;
+ case 0xaf: sts_ix(); break;
+ case 0xb0: suba_ex(); break;
+ case 0xb1: cmpa_ex(); break;
+ case 0xb2: sbca_ex(); break;
+ case 0xb3: illegal(); break;
+ case 0xb4: anda_ex(); break;
+ case 0xb5: bita_ex(); break;
+ case 0xb6: lda_ex(); break;
+ case 0xb7: sta_ex(); break;
+ case 0xb8: eora_ex(); break;
+ case 0xb9: adca_ex(); break;
+ case 0xba: ora_ex(); break;
+ case 0xbb: adda_ex(); break;
+ case 0xbc: cmpx_ex(); break;
+ case 0xbd: jsr_ex(); break;
+ case 0xbe: lds_ex(); break;
+ case 0xbf: sts_ex(); break;
+ case 0xc0: subb_im(); break;
+ case 0xc1: cmpb_im(); break;
+ case 0xc2: sbcb_im(); break;
+ case 0xc3: illegal(); break;
+ case 0xc4: andb_im(); break;
+ case 0xc5: bitb_im(); break;
+ case 0xc6: ldb_im(); break;
+ case 0xc7: stb_im(); break;
+ case 0xc8: eorb_im(); break;
+ case 0xc9: adcb_im(); break;
+ case 0xca: orb_im(); break;
+ case 0xcb: addb_im(); break;
+ case 0xcc: illegal(); break;
+ case 0xcd: illegal(); break;
+ case 0xce: ldx_im(); break;
+ case 0xcf: stx_im(); break;
+ case 0xd0: subb_di(); break;
+ case 0xd1: cmpb_di(); break;
+ case 0xd2: sbcb_di(); break;
+ case 0xd3: illegal(); break;
+ case 0xd4: andb_di(); break;
+ case 0xd5: bitb_di(); break;
+ case 0xd6: ldb_di(); break;
+ case 0xd7: stb_di(); break;
+ case 0xd8: eorb_di(); break;
+ case 0xd9: adcb_di(); break;
+ case 0xda: orb_di(); break;
+ case 0xdb: addb_di(); break;
+ case 0xdc: illegal(); break;
+ case 0xdd: illegal(); break;
+ case 0xde: ldx_di(); break;
+ case 0xdf: stx_di(); break;
+ case 0xe0: subb_ix(); break;
+ case 0xe1: cmpb_ix(); break;
+ case 0xe2: sbcb_ix(); break;
+ case 0xe3: illegal(); break;
+ case 0xe4: andb_ix(); break;
+ case 0xe5: bitb_ix(); break;
+ case 0xe6: ldb_ix(); break;
+ case 0xe7: stb_ix(); break;
+ case 0xe8: eorb_ix(); break;
+ case 0xe9: adcb_ix(); break;
+ case 0xea: orb_ix(); break;
+ case 0xeb: addb_ix(); break;
+
+ case 0xec: adx_im(); break;
+
+ case 0xed: illegal(); break;
+ case 0xee: ldx_ix(); break;
+ case 0xef: stx_ix(); break;
+ case 0xf0: subb_ex(); break;
+ case 0xf1: cmpb_ex(); break;
+ case 0xf2: sbcb_ex(); break;
+ case 0xf3: illegal(); break;
+ case 0xf4: andb_ex(); break;
+ case 0xf5: bitb_ex(); break;
+ case 0xf6: ldb_ex(); break;
+ case 0xf7: stb_ex(); break;
+ case 0xf8: eorb_ex(); break;
+ case 0xf9: adcb_ex(); break;
+ case 0xfa: orb_ex(); break;
+ case 0xfb: addb_ex(); break;
+
+ case 0xfc: adx_ex(); break;
+
+ case 0xfd: illegal(); break;
+ case 0xfe: ldx_ex(); break;
+ case 0xff: stx_ex(); break;
+#if defined(_MSC_VER) && (_MSC_VER >= 1200)
+ default: __assume(0);
+#endif
+ }
+}
+
+/* operate one instruction for */
+#define ONE_MORE_INSN() { \
+ uint8_t ireg = M_RDOP(PCD); \
+ prevpc = PC; \
+ PC++; \
+ insn(ireg); \
+ increment_counter(cycles[ireg]); \
+}
+
+/* $71 NIM --**0- */ /* MB8861 only */
+void MB8861::nim_ix()
+{
+ uint8_t t, r;
+ IMMBYTE(t);
+ IDXBYTE(r);
+ r &= t;
+ CLR_NZV;
+ if(!r) {
+ SEZ;
+ } else {
+ SEN;
+ }
+ WM(EAD, r);
+}
+
+
+/* $72 OIM --**0- */ /* MB8861 only */
+void MB8861::oim_ix_mb8861()
+{
+ uint8_t t, r;
+ IMMBYTE(t);
+ IDXBYTE(r);
+ r |= t;
+ CLR_NZV;
+ if(!r) {
+ SEZ;
+ } else {
+ SEN;
+ }
+ WM(EAD, r);
+}
+
+/* $75 XIM --**-- */ /* MB8861 only */
+void MB8861::xim_ix()
+{
+ uint8_t t, r;
+ IMMBYTE(t);
+ IDXBYTE(r);
+ r ^= t;
+ CLR_NZ;
+ if(!r) {
+ SEZ;
+ } else {
+ SEN;
+ }
+ WM(EAD, r);
+}
+
+/* $7b TMM --***- */ /* MB8861 only */
+void MB8861::tmm_ix()
+{
+ uint8_t t, r;
+ IMMBYTE(t);
+ IDXBYTE(r);
+ r &= t;
+ CLR_NZV;
+ if(!t || !r) {
+ SEZ;
+ } else if(r == t) {
+ SEV;
+ } else {
+ SEN;
+ }
+}
+
+/* $ec ADX immediate -**** */ /* MB8861 only */
+void MB8861::adx_im()
+{
+ uint32_t r, d, t;
+ IMMBYTE(t);
+ d = X;
+ r = d + t;
+ CLR_NZVC;
+ SET_FLAGS16(d, t, r);
+ X = r;
+}
+
+/* $fc ADX immediate -**** */ /* MB8861 only */
+void MB8861::adx_ex()
+{
+ uint32_t r, d;
+ pair_t b;
+ EXTWORD(b);
+ d = X;
+ r = d + b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+ X = r;
+}
+
--- /dev/null
+#ifndef _MB8861_H_
+#define _MB8861_H_
+
+#include "mc6800.h"
+#include "device.h"
+
+class DEBUGGER;
+class FIFO;
+//#endif
+class MB8861 : public MC6800
+{
+private:
+#define XX 5 // invalid opcode unknown cc
+ const uint8_t cycles[256] = {
+ XX, 2,XX,XX,XX,XX, 2, 2, 4, 4, 2, 2, 2, 2, 2, 2,
+ 2, 2,XX,XX,XX,XX, 2, 2,XX, 2,XX, 2,XX,XX,XX,XX,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4,XX, 5,XX,10,XX,XX, 9,12,
+ 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
+ 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
+ 7,XX,XX, 7, 7,XX, 7, 7, 7, 7, 7,XX, 7, 7, 4, 7,
+ 6, 8, 8, 6, 6, 8, 6, 6, 6, 6, 6, 7, 6, 6, 3, 6,
+ 2, 2, 2,XX, 2, 2, 2, 3, 2, 2, 2, 2, 3, 8, 3, 4,
+ 3, 3, 3,XX, 3, 3, 3, 4, 3, 3, 3, 3, 4, 6, 4, 5,
+ 5, 5, 5,XX, 5, 5, 5, 6, 5, 5, 5, 5, 6, 8, 6, 7,
+ 4, 4, 4,XX, 4, 4, 4, 5, 4, 4, 4, 4, 5, 9, 5, 6,
+ 2, 2, 2,XX, 2, 2, 2, 3, 2, 2, 2, 2,XX,XX, 3, 4,
+ 3, 3, 3,XX, 3, 3, 3, 4, 3, 3, 3, 3,XX,XX, 4, 5,
+ 5, 5, 5,XX, 5, 5, 5, 6, 5, 5, 5, 5, 4,XX, 6, 7,
+ 4, 4, 4,XX, 4, 4, 4, 5, 4, 4, 4, 4, 7,XX, 5, 6
+ };
+#undef XX // invalid opcode unknown cc
+protected:
+ void insn(uint8_t code) override;
+
+ void nim_ix();
+ void oim_ix_mb8861();
+ void xim_ix();
+ void tmm_ix();
+ void adx_im();
+ void adx_ex();
+
+public:
+ MB8861(VM* parent_vm, EMU* parent_emu) : MC6800(parent_vm, parent_emu)
+ {
+ set_device_name(_T("MB8861 MPU"));
+ }
+ ~MB8861() {}
+ int debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len) override;
+
+
+};
+
+#endif
#endif
#include "mc6800.h"
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
-#include "../fifo.h"
-#endif
-#ifdef USE_DEBUGGER
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+//#include "../fifo.h"
+//#endif
+//#ifdef USE_DEBUGGER
#include "debugger.h"
-#endif
-
-#define INT_REQ_BIT 1
-#define NMI_REQ_BIT 2
-
-#define MC6800_WAI 8
-#define HD6301_SLP 0x10
+//#endif
+#include "mc6800_consts.h"
-#define pPC pc
-#define pS sp
-#define pX ix
-#define pD acc_d
-#define pEA ea
-
-#define PC pc.w.l
-#define PCD pc.d
-#define S sp.w.l
-#define SD sp.d
-#define X ix.w.l
-#define D acc_d.w.l
-#define A acc_d.b.h
-#define B acc_d.b.l
-#define CC cc
-
-#define EAD ea.d
-#define EA ea.w.l
/****************************************************************************/
/* memory */
uint32_t MC6800::RM(uint32_t Addr)
{
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- if(Addr < 0x20) {
- return mc6801_io_r(Addr);
- } else if(Addr >= 0x80 && Addr < 0x100 && (ram_ctrl & 0x40)) {
- return ram[Addr & 0x7f];
- }
-#endif
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// if(Addr < 0x20) {
+// return mc6801_io_r(Addr);
+// } else if(Addr >= 0x80 && Addr < 0x100 && (ram_ctrl & 0x40)) {
+// return ram[Addr & 0x7f];
+// }
+//#endif
return d_mem->read_data8(Addr);
}
void MC6800::WM(uint32_t Addr, uint32_t Value)
{
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- if(Addr < 0x20) {
- mc6801_io_w(Addr, Value);
- } else if(Addr >= 0x80 && Addr < 0x100 && (ram_ctrl & 0x40)) {
- ram[Addr & 0x7f] = Value;
- } else
-#endif
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// if(Addr < 0x20) {
+// mc6801_io_w(Addr, Value);
+// } else if(Addr >= 0x80 && Addr < 0x100 && (ram_ctrl & 0x40)) {
+// ram[Addr & 0x7f] = Value;
+// } else
+//#endif
d_mem->write_data8(Addr, Value);
}
WM((Addr + 1) & 0xffff, p->b.l);
}
-//#define M_RDOP(Addr) d_mem->read_data8(Addr)
-//#define M_RDOP_ARG(Addr) d_mem->read_data8(Addr)
-#define M_RDOP(Addr) RM(Addr)
-#define M_RDOP_ARG(Addr) RM(Addr)
-
-/* macros to access memory */
-#define IMMBYTE(b) b = M_RDOP_ARG(PCD); PC++
-#define IMMWORD(w) w.b.h = M_RDOP_ARG(PCD); w.b.l = M_RDOP_ARG((PCD + 1) & 0xffff); PC += 2
-
-#define PUSHBYTE(b) WM(SD, b); --S
-#define PUSHWORD(w) WM(SD, w.b.l); --S; WM(SD, w.b.h); --S
-#define PULLBYTE(b) S++; b = RM(SD)
-#define PULLWORD(w) S++; w.b.h = RM(SD); S++; w.b.l = RM(SD)
-
-/****************************************************************************/
-/* MC6801/HD6301 internal i/o port */
-/****************************************************************************/
-
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
-
-#define CT counter.w.l
-#define CTH counter.w.h
-#define CTD counter.d
-#define OC output_compare.w.l
-#define OCH output_compare.w.h
-#define OCD output_compare.d
-#define TOH timer_over.w.l
-#define TOD timer_over.d
-
-#define SET_TIMER_EVENT { \
- timer_next = (OCD - CTD < TOD - CTD) ? OCD : TOD; \
-}
-
-#define CLEANUP_COUNTERS() { \
- OCH -= CTH; \
- TOH -= CTH; \
- CTH = 0; \
- SET_TIMER_EVENT; \
-}
-
-#define MODIFIED_counters { \
- OCH = (OC >= CT) ? CTH : CTH + 1; \
- SET_TIMER_EVENT; \
-}
-
-#define TCSR_OLVL 0x01
-#define TCSR_IEDG 0x02
-#define TCSR_ETOI 0x04
-#define TCSR_EOCI 0x08
-#define TCSR_EICI 0x10
-#define TCSR_TOF 0x20
-#define TCSR_OCF 0x40
-#define TCSR_ICF 0x80
-
-#define TRCSR_WU 0x01
-#define TRCSR_TE 0x02
-#define TRCSR_TIE 0x04
-#define TRCSR_RE 0x08
-#define TRCSR_RIE 0x10
-#define TRCSR_TDRE 0x20
-#define TRCSR_ORFE 0x40
-#define TRCSR_RDRF 0x80
-
-#define P3CSR_LE 0x08
-#define P3CSR_IS3_ENABLE 0x40
-#define P3CSR_IS3_FLAG 0x80
-
-static const int RMCR_SS[] = { 16, 128, 1024, 4096 };
-
-/* take interrupt */
-#define TAKE_ICI enter_interrupt(0xfff6)
-#define TAKE_OCI enter_interrupt(0xfff4)
-#define TAKE_TOI enter_interrupt(0xfff2)
-#define TAKE_SCI enter_interrupt(0xfff0)
-#define TAKE_TRAP enter_interrupt(0xffee)
-
-uint32_t MC6800::mc6801_io_r(uint32_t offset)
-{
- switch (offset) {
- case 0x00:
- // port1 data direction register
- return port[0].ddr;
- case 0x01:
- // port2 data direction register
- return port[1].ddr;
- case 0x02:
- // port1 data register
- return (port[0].rreg & ~port[0].ddr) | (port[0].wreg & port[0].ddr);
- case 0x03:
- // port2 data register
- return (port[1].rreg & ~port[1].ddr) | (port[1].wreg & port[1].ddr);
- case 0x04:
- // port3 data direction register (write only???)
- return port[2].ddr;
- case 0x05:
- // port4 data direction register
- return port[3].ddr;
- case 0x06:
- // port3 data register
- if(p3csr_is3_flag_read) {
- p3csr_is3_flag_read = false;
- p3csr &= ~P3CSR_IS3_FLAG;
- }
- if(port[2].latched) {
- port[2].latched = false;
- return (port[2].latched_data & ~port[2].ddr) | (port[2].wreg & port[2].ddr);
- }
- return (port[2].rreg & ~port[2].ddr) | (port[2].wreg & port[2].ddr);
- case 0x07:
- // port4 data register
- return (port[3].rreg & ~port[3].ddr) | (port[3].wreg & port[3].ddr);
- case 0x08:
- // timer control register
- pending_tcsr = 0;
- return tcsr;
- case 0x09:
- // free running counter (msb)
- if(!(pending_tcsr & TCSR_TOF)) {
- tcsr &= ~TCSR_TOF;
- }
- return counter.b.h;
- case 0x0a:
- // free running counter (lsb)
- return counter.b.l;
- case 0x0b:
- // output compare register (msb)
- if(!(pending_tcsr & TCSR_OCF)) {
- tcsr &= ~TCSR_OCF;
- }
- return output_compare.b.h;
- case 0x0c:
- // output compare register (lsb)
- if(!(pending_tcsr & TCSR_OCF)) {
- tcsr &= ~TCSR_OCF;
- }
- return output_compare.b.l;
- case 0x0d:
- // input capture register (msb)
- if(!(pending_tcsr & TCSR_ICF)) {
- tcsr &= ~TCSR_ICF;
- }
- return (input_capture >> 0) & 0xff;
- case 0x0e:
- // input capture register (lsb)
- return (input_capture >> 8) & 0xff;
- case 0x0f:
- // port3 control/status register
- p3csr_is3_flag_read = true;
- return p3csr;
- case 0x10:
- // rate and mode control register
- return rmcr;
- case 0x11:
- if(trcsr & TRCSR_TDRE) {
- trcsr_read_tdre = true;
- }
- if(trcsr & TRCSR_ORFE) {
- trcsr_read_orfe = true;
- }
- if(trcsr & TRCSR_RDRF) {
- trcsr_read_rdrf = true;
- }
- return trcsr;
- case 0x12:
- // receive data register
- if(trcsr_read_orfe) {
- trcsr_read_orfe = false;
- trcsr &= ~TRCSR_ORFE;
- }
- if(trcsr_read_rdrf) {
- trcsr_read_rdrf = false;
- trcsr &= ~TRCSR_RDRF;
- }
- return rdr;
- case 0x13:
- // transmit data register
- return tdr;
- case 0x14:
- // ram control register
- return (ram_ctrl & 0x40) | 0x3f;
- }
- return 0;
-}
-
-void MC6800::mc6801_io_w(uint32_t offset, uint32_t data)
-{
- switch(offset) {
- case 0x00:
- // port1 data direction register
- port[0].ddr = data;
- break;
- case 0x01:
- // port2 data direction register
- port[1].ddr = data;
- break;
- case 0x02:
- // port1 data register
- if(port[0].wreg != data || port[0].first_write) {
- write_signals(&port[0].outputs, data);
- port[0].wreg = data;
- port[0].first_write = false;
- }
- break;
- case 0x03:
- // port2 data register
- if(port[1].wreg != data || port[1].first_write) {
- write_signals(&port[1].outputs, data);
- port[1].wreg = data;
- port[1].first_write = false;
- }
- break;
- case 0x04:
- // port3 data direction register
- port[2].ddr = data;
- break;
- case 0x05:
- // port4 data direction register
- port[3].ddr = data;
- break;
- case 0x06:
- // port3 data register
- if(p3csr_is3_flag_read) {
- p3csr_is3_flag_read = false;
- p3csr &= ~P3CSR_IS3_FLAG;
- }
- if(port[2].wreg != data || port[2].first_write) {
- write_signals(&port[2].outputs, data);
- port[2].wreg = data;
- port[2].first_write = false;
- }
- break;
- case 0x07:
- // port4 data register
- if(port[3].wreg != data || port[3].first_write) {
- write_signals(&port[3].outputs, data);
- port[3].wreg = data;
- port[3].first_write = false;
- }
- break;
- case 0x08:
- // timer control/status register
- tcsr = data;
- pending_tcsr &= tcsr;
- break;
- case 0x09:
- // free running counter (msb)
-#ifdef HAS_HD6301
- latch09 = data & 0xff;
-#endif
- CT = 0xfff8;
- TOH = CTH;
- MODIFIED_counters;
- break;
-#ifdef HAS_HD6301
- case 0x0a:
- // free running counter (lsb)
- CT = (latch09 << 8) | (data & 0xff);
- TOH = CTH;
- MODIFIED_counters;
- break;
-#endif
- case 0x0b:
- // output compare register (msb)
- if(output_compare.b.h != data) {
- output_compare.b.h = data;
- MODIFIED_counters;
- }
- tcsr &=~TCSR_OCF;
- break;
- case 0x0c:
- // output compare register (lsb)
- if(output_compare.b.l != data) {
- output_compare.b.l = data;
- MODIFIED_counters;
- }
- tcsr &=~TCSR_OCF;
- break;
- case 0x0f:
- // port3 control/status register
- p3csr = (p3csr & P3CSR_IS3_FLAG) | (data & ~P3CSR_IS3_FLAG);
- break;
- case 0x10:
- // rate and mode control register
- rmcr = data;
- break;
- case 0x11:
- // transmit/receive control/status register
- trcsr = (trcsr & 0xe0) | (data & 0x1f);
- break;
- case 0x13:
- // transmit data register
- if(trcsr_read_tdre) {
- trcsr_read_tdre = false;
- trcsr &= ~TRCSR_TDRE;
- }
- tdr = data;
- break;
- case 0x14:
- // ram control register
- ram_ctrl = data;
- break;
- }
-}
-
-void MC6800::increment_counter(int amount)
-{
- icount -= amount;
-
- // timer
- if((CTD += amount) >= timer_next) {
- /* OCI */
- if( CTD >= OCD) {
- OCH++; // next IRQ point
- tcsr |= TCSR_OCF;
- pending_tcsr |= TCSR_OCF;
- }
- /* TOI */
- if( CTD >= TOD) {
- TOH++; // next IRQ point
- tcsr |= TCSR_TOF;
- pending_tcsr |= TCSR_TOF;
- }
- /* set next event */
- SET_TIMER_EVENT;
- }
-
- // serial i/o
- if((sio_counter -= amount) <= 0) {
- if((trcsr & TRCSR_TE) && !(trcsr & TRCSR_TDRE)) {
- write_signals(&outputs_sio, tdr);
- trcsr |= TRCSR_TDRE;
- }
- if((trcsr & TRCSR_RE) && !recv_buffer->empty()) {
- if(trcsr & TRCSR_WU) {
- // skip 10 bits
- trcsr &= ~TRCSR_WU;
- recv_buffer->read();
- } else if(!(trcsr & TRCSR_RDRF)) {
- // note: wait reveived data is read by cpu, so overrun framing error never occurs
- rdr = recv_buffer->read();
- trcsr |= TRCSR_RDRF;
- }
- }
- sio_counter += RMCR_SS[rmcr & 3];
- }
-}
-
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+//#else
#define increment_counter(amount) icount -= amount
+//#endif
-#endif
-#define CLR_HNZVC CC &= 0xd0
-#define CLR_NZV CC &= 0xf1
-#define CLR_HNZC CC &= 0xd2
-#define CLR_NZVC CC &= 0xf0
-#define CLR_NZ CC &= 0xf3
-#define CLR_Z CC &= 0xfb
-#define CLR_NZC CC &= 0xf2
-#define CLR_ZC CC &= 0xfa
-#define CLR_C CC &= 0xfe
-
-#define SET_Z(a) if(!(a)) SEZ
-#define SET_Z8(a) SET_Z((uint8_t)(a))
-#define SET_Z16(a) SET_Z((uint16_t)(a))
-#define SET_N8(a) CC |= (((a) & 0x80) >> 4)
-#define SET_N16(a) CC |= (((a) & 0x8000) >> 12)
-#define SET_H(a,b,r) CC |= ((((a) ^ (b) ^ (r)) & 0x10) << 1)
-#define SET_C8(a) CC |= (((a) & 0x100) >> 8)
-#define SET_C16(a) CC |= (((a) & 0x10000) >> 16)
-#define SET_V8(a,b,r) CC |= ((((a) ^ (b) ^ (r) ^ ((r) >> 1)) & 0x80) >> 6)
-#define SET_V16(a,b,r) CC |= ((((a) ^ (b) ^ (r) ^ ((r) >> 1)) & 0x8000) >> 14)
-
-static const uint8_t flags8i[256] = {
+static const uint8_t MC6800::flags8i[256] = {
/* increment */
0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08
};
-static const uint8_t flags8d[256] = {
+static const uint8_t MC6800::flags8d[256] = {
/* decrement */
0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08
};
-#define SET_FLAGS8I(a) {CC |= flags8i[(a) & 0xff];}
-#define SET_FLAGS8D(a) {CC |= flags8d[(a) & 0xff];}
-
-/* combos */
-#define SET_NZ8(a) {SET_N8(a); SET_Z8(a);}
-#define SET_NZ16(a) {SET_N16(a); SET_Z16(a);}
-#define SET_FLAGS8(a,b,r) {SET_N8(r); SET_Z8(r); SET_V8(a,b,r); SET_C8(r); }
-#define SET_FLAGS16(a,b,r) {SET_N16(r); SET_Z16(r); SET_V16(a,b,r); SET_C16(r);}
-
-/* for treating an uint8_t as a signed int16_t */
-#define SIGNED(b) ((int16_t)(b & 0x80 ? b | 0xff00 : b))
-
-/* Macros for addressing modes */
-#define DIRECT IMMBYTE(EAD)
-#define IMM8 EA = PC++
-#define IMM16 {EA = PC; PC += 2;}
-#define EXTENDED IMMWORD(pEA)
-#define INDEXED {EA = X + (uint8_t)M_RDOP_ARG(PCD); PC++;}
-
-/* macros to set status flags */
-#define SEC CC |= 0x01
-#define CLC CC &= 0xfe
-#define SEZ CC |= 0x04
-#define CLZ CC &= 0xfb
-#define SEN CC |= 0x08
-#define CLN CC &= 0xf7
-#define SEV CC |= 0x02
-#define CLV CC &= 0xfd
-#define SEH CC |= 0x20
-#define CLH CC &= 0xdf
-#define SEI CC |= 0x10
-#define CLI CC &= ~0x10
-
-/* macros for convenience */
-#define DIRBYTE(b) {DIRECT; b = RM(EAD); }
-#define DIRWORD(w) {DIRECT; w.d = RM16(EAD);}
-#define EXTBYTE(b) {EXTENDED; b = RM(EAD); }
-#define EXTWORD(w) {EXTENDED; w.d = RM16(EAD);}
-
-#define IDXBYTE(b) {INDEXED; b = RM(EAD); }
-#define IDXWORD(w) {INDEXED; w.d = RM16(EAD);}
-
-/* Macros for branch instructions */
-#define BRANCH(f) {IMMBYTE(t); if(f) {PC += SIGNED(t);}}
-#define NXORV ((CC & 0x08) ^ ((CC & 0x02) << 2))
-
-/* Note: don't use 0 cycles here for invalid opcodes so that we don't */
-/* hang in an infinite loop if we hit one */
-#define XX 5 // invalid opcode unknown cc
-static const uint8_t cycles[] = {
-#if defined(HAS_MC6800)
- XX, 2,XX,XX,XX,XX, 2, 2, 4, 4, 2, 2, 2, 2, 2, 2,
- 2, 2,XX,XX,XX,XX, 2, 2,XX, 2,XX, 2,XX,XX,XX,XX,
- 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
- 4, 4, 4, 4, 4, 4, 4, 4,XX, 5,XX,10,XX,XX, 9,12,
- 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
- 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
- 7,XX,XX, 7, 7,XX, 7, 7, 7, 7, 7,XX, 7, 7, 4, 7,
- 6,XX,XX, 6, 6,XX, 6, 6, 6, 6, 6,XX, 6, 6, 3, 6,
- 2, 2, 2,XX, 2, 2, 2, 3, 2, 2, 2, 2, 3, 8, 3, 4,
- 3, 3, 3,XX, 3, 3, 3, 4, 3, 3, 3, 3, 4, 6, 4, 5,
- 5, 5, 5,XX, 5, 5, 5, 6, 5, 5, 5, 5, 6, 8, 6, 7,
- 4, 4, 4,XX, 4, 4, 4, 5, 4, 4, 4, 4, 5, 9, 5, 6,
- 2, 2, 2,XX, 2, 2, 2, 3, 2, 2, 2, 2,XX,XX, 3, 4,
- 3, 3, 3,XX, 3, 3, 3, 4, 3, 3, 3, 3,XX,XX, 4, 5,
- 5, 5, 5,XX, 5, 5, 5, 6, 5, 5, 5, 5,XX,XX, 6, 7,
- 4, 4, 4,XX, 4, 4, 4, 5, 4, 4, 4, 4,XX,XX, 5, 6
-#elif defined(HAS_MC6801)
- XX, 2,XX,XX, 3, 3, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2,
- 2, 2,XX,XX,XX,XX, 2, 2,XX, 2,XX, 2,XX,XX,XX,XX,
- 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
- 3, 3, 4, 4, 3, 3, 3, 3, 5, 5, 3,10, 4,10, 9,12,
- 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
- 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
- 6,XX,XX, 6, 6,XX, 6, 6, 6, 6, 6,XX, 6, 6, 3, 6,
- 6,XX,XX, 6, 6,XX, 6, 6, 6, 6, 6,XX, 6, 6, 3, 6,
- 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 4, 6, 3, 3,
- 3, 3, 3, 5, 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 4, 4,
- 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 5, 5,
- 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 5, 5,
- 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 3,XX, 3, 3,
- 3, 3, 3, 5, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4,
- 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
- 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5
-#elif defined(HAS_HD6301)
- XX, 1,XX,XX, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1,XX,XX,XX,XX, 1, 1, 2, 2, 4, 1,XX,XX,XX,XX,
- 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
- 1, 1, 3, 3, 1, 1, 4, 4, 4, 5, 1,10, 5, 7, 9,12,
- 1,XX,XX, 1, 1,XX, 1, 1, 1, 1, 1,XX, 1, 1,XX, 1,
- 1,XX,XX, 1, 1,XX, 1, 1, 1, 1, 1,XX, 1, 1,XX, 1,
- 6, 7, 7, 6, 6, 7, 6, 6, 6, 6, 6, 5, 6, 4, 3, 5,
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 4, 6, 4, 3, 5,
- 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 2, 3, 5, 3, 3,
- 3, 3, 3, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 5, 4, 4,
- 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
- 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 6, 5, 5,
- 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 2, 3,XX, 3, 3,
- 3, 3, 3, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4,
- 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
- 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5
-#elif defined(HAS_MB8861)
- XX, 2,XX,XX,XX,XX, 2, 2, 4, 4, 2, 2, 2, 2, 2, 2,
- 2, 2,XX,XX,XX,XX, 2, 2,XX, 2,XX, 2,XX,XX,XX,XX,
- 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
- 4, 4, 4, 4, 4, 4, 4, 4,XX, 5,XX,10,XX,XX, 9,12,
- 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
- 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
- 7,XX,XX, 7, 7,XX, 7, 7, 7, 7, 7,XX, 7, 7, 4, 7,
- 6, 8, 8, 6, 6, 8, 6, 6, 6, 6, 6, 7, 6, 6, 3, 6,
- 2, 2, 2,XX, 2, 2, 2, 3, 2, 2, 2, 2, 3, 8, 3, 4,
- 3, 3, 3,XX, 3, 3, 3, 4, 3, 3, 3, 3, 4, 6, 4, 5,
- 5, 5, 5,XX, 5, 5, 5, 6, 5, 5, 5, 5, 6, 8, 6, 7,
- 4, 4, 4,XX, 4, 4, 4, 5, 4, 4, 4, 4, 5, 9, 5, 6,
- 2, 2, 2,XX, 2, 2, 2, 3, 2, 2, 2, 2,XX,XX, 3, 4,
- 3, 3, 3,XX, 3, 3, 3, 4, 3, 3, 3, 3,XX,XX, 4, 5,
- 5, 5, 5,XX, 5, 5, 5, 6, 5, 5, 5, 5, 4,XX, 6, 7,
- 4, 4, 4,XX, 4, 4, 4, 5, 4, 4, 4, 4, 7,XX, 5, 6
-#endif
-};
-#undef XX // invalid opcode unknown cc
void MC6800::initialize()
{
DEVICE::initialize();
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- recv_buffer = new FIFO(0x10000);
- ram_ctrl = 0xc0;
-#endif
-#ifdef USE_DEBUGGER
- d_mem_stored = d_mem;
- d_debugger->set_context_mem(d_mem);
-#endif
+ __USE_DEBUGGER = osd->check_feature(_T("USE_DEBUGGER"));
+ if(__USE_DEBUGGER) {
+//#ifdef USE_DEBUGGER
+ d_mem_stored = d_mem;
+ d_debugger->set_context_mem(d_mem);
+//#endif
+ } else {
+ d_mem_stored = NULL;
+ }
}
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
-void MC6800::release()
-{
- recv_buffer->release();
- delete recv_buffer;
-}
-#endif
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+//void MC6800::release()
+//{
+// recv_buffer->release();
+// delete recv_buffer;
+//}
+//#endif
void MC6800::reset()
{
icount = 0;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- for(int i = 0; i < 4; i++) {
- port[i].ddr = 0x00;
- port[i].first_write = true;
- port[i].latched = false;
- }
- p3csr = 0x00;
- p3csr_is3_flag_read = false;
- sc1_state = sc2_state = false;
-
- tcsr = pending_tcsr = 0x00;
- CTD = 0x0000;
- OCD = 0xffff;
- TOD = 0xffff;
-
- recv_buffer->clear();
- trcsr = TRCSR_TDRE;
- trcsr_read_tdre = trcsr_read_orfe = trcsr_read_rdrf = false;
- rmcr = 0x00;
- sio_counter = RMCR_SS[rmcr & 3];
-
- ram_ctrl |= 0x40;
-#endif
}
void MC6800::write_signal(int id, uint32_t data, uint32_t mask)
int_state &= ~NMI_REQ_BIT;
}
break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case SIG_MC6801_PORT_1:
- port[0].rreg = (port[0].rreg & ~mask) | (data & mask);
- break;
- case SIG_MC6801_PORT_2:
- if((mask & 1) && (port[1].rreg & 1) != (data & 1) && (tcsr & 2) == ((data << 1) & 2)) {
- // active TIN edge in
- tcsr |= TCSR_ICF;
- pending_tcsr |= TCSR_ICF;
- input_capture = CT;
- }
- port[1].rreg = (port[1].rreg & ~mask) | (data & mask);
- break;
- case SIG_MC6801_PORT_3:
- port[2].rreg = (port[2].rreg & ~mask) | (data & mask);
- break;
- case SIG_MC6801_PORT_4:
- port[3].rreg = (port[3].rreg & ~mask) | (data & mask);
- break;
- case SIG_MC6801_PORT_3_SC1:
- if(sc1_state && !(data & mask)) {
- // SC1: H -> L
- if(!port[2].latched && (p3csr & P3CSR_LE)) {
- port[2].latched_data = port[2].rreg;
- port[2].latched = true;
- p3csr |= P3CSR_IS3_FLAG;
- }
- }
- sc1_state = ((data & mask) != 0);
- break;
- case SIG_MC6801_PORT_3_SC2:
- sc2_state = ((data & mask) != 0);
- break;
- case SIG_MC6801_SIO_RECV:
- recv_buffer->write(data & mask);
- break;
-#endif
}
}
// run cpu
if(clock == -1) {
// run only one opcode
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- CLEANUP_COUNTERS();
-#endif
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// CLEANUP_COUNTERS();
+//#endif
icount = 0;
-#ifdef USE_DEBUGGER
- bool now_debugging = d_debugger->now_debugging;
- if(now_debugging) {
- d_debugger->check_break_points(PC);
- if(d_debugger->now_suspended) {
- emu->mute_sound();
- while(d_debugger->now_debugging && d_debugger->now_suspended) {
- emu->sleep(10);
- }
- }
- if(d_debugger->now_debugging) {
- d_mem = d_debugger;
- } else {
- now_debugging = false;
- }
-
- run_one_opecode();
-
- if(now_debugging) {
- if(!d_debugger->now_going) {
- d_debugger->now_suspended = true;
- }
- d_mem = d_mem_stored;
- }
- } else {
-#endif
- run_one_opecode();
-#ifdef USE_DEBUGGER
- }
-#endif
- return -icount;
- } else {
- /* run cpu while given clocks */
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- CLEANUP_COUNTERS();
-#endif
- icount += clock;
- int first_icount = icount;
-
- while(icount > 0) {
-#ifdef USE_DEBUGGER
+//#ifdef USE_DEBUGGER
+ if(__USE_DEBUGGER) {
bool now_debugging = d_debugger->now_debugging;
if(now_debugging) {
d_debugger->check_break_points(PC);
}
d_mem = d_mem_stored;
}
+
} else {
-#endif
+//#endif
run_one_opecode();
-#ifdef USE_DEBUGGER
}
-#endif
+ } else {
+ run_one_opecode();
+//#ifdef USE_DEBUGGER
}
- return first_icount - icount;
+//#endif
+ return -icount;
}
+ /* run cpu while given clocks */
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// CLEANUP_COUNTERS();
+//#endif
+ icount += clock;
+ int first_icount = icount;
+
+ while(icount > 0) {
+//#ifdef USE_DEBUGGER
+ if(__USE_DEBUGGER) {
+ bool now_debugging = d_debugger->now_debugging;
+ if(now_debugging) {
+ d_debugger->check_break_points(PC);
+ if(d_debugger->now_suspended) {
+ emu->mute_sound();
+ while(d_debugger->now_debugging && d_debugger->now_suspended) {
+ emu->sleep(10);
+ }
+ }
+ if(d_debugger->now_debugging) {
+ d_mem = d_debugger;
+ } else {
+ now_debugging = false;
+ }
+
+ run_one_opecode();
+
+ if(now_debugging) {
+ if(!d_debugger->now_going) {
+ d_debugger->now_suspended = true;
+ }
+ d_mem = d_mem_stored;
+ }
+ } else {
+//#endif
+ run_one_opecode();
+ }
+ } else {
+ run_one_opecode();
+//#ifdef USE_DEBUGGER
+ }
+//#endif
+ }
+ return first_icount - icount;
}
+
void MC6800::run_one_opecode()
{
if(wai_state & (MC6800_WAI | HD6301_SLP)) {
int_state &= ~INT_REQ_BIT;
enter_interrupt(0xfff8);
}
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- } else if((tcsr & (TCSR_EICI | TCSR_ICF)) == (TCSR_EICI | TCSR_ICF)) {
- wai_state &= ~HD6301_SLP;
- if(!(CC & 0x10)) {
- TAKE_ICI;
- }
- } else if((tcsr & (TCSR_EOCI | TCSR_OCF)) == (TCSR_EOCI | TCSR_OCF)) {
- wai_state &= ~HD6301_SLP;
- if(!(CC & 0x10)) {
- TAKE_OCI;
- }
- } else if((tcsr & (TCSR_ETOI | TCSR_TOF)) == (TCSR_ETOI | TCSR_TOF)) {
- wai_state &= ~HD6301_SLP;
- if(!(CC & 0x10)) {
- TAKE_TOI;
- }
- } else if(((trcsr & (TRCSR_RIE | TRCSR_RDRF)) == (TRCSR_RIE | TRCSR_RDRF)) ||
- ((trcsr & (TRCSR_RIE | TRCSR_ORFE)) == (TRCSR_RIE | TRCSR_ORFE)) ||
- ((trcsr & (TRCSR_TIE | TRCSR_TDRE)) == (TRCSR_TIE | TRCSR_TDRE))) {
- wai_state &= ~HD6301_SLP;
- if(!(CC & 0x10)) {
- TAKE_SCI;
- }
-#endif
}
}
-#ifdef USE_DEBUGGER
+//#ifdef USE_DEBUGGER
void MC6800::write_debug_data8(uint32_t addr, uint32_t data)
{
int wait;
+ if(d_mem_stored == NULL) return;
d_mem_stored->write_data8w(addr, data, &wait);
}
uint32_t MC6800::read_debug_data8(uint32_t addr)
{
int wait;
+ if(d_mem_stored == NULL) return 0xff;
return d_mem_stored->read_data8w(addr, &wait);
}
void MC6800::write_debug_data16(uint32_t addr, uint32_t data)
{
+ if(d_mem_stored == NULL) return;
write_debug_data8(addr, (data >> 8) & 0xff);
write_debug_data8(addr + 1, data & 0xff);
}
uint32_t MC6800::read_debug_data16(uint32_t addr)
{
+ if(d_mem_stored == NULL) return 0xffff;
uint32_t val = read_debug_data8(addr) << 8;
val |= read_debug_data8(addr + 1);
return val;
void MC6800::write_debug_data32(uint32_t addr, uint32_t data)
{
+ if(d_mem_stored == NULL) return;
write_debug_data16(addr, (data >> 16) & 0xffff);
write_debug_data16(addr + 2, data & 0xffff);
}
uint32_t MC6800::read_debug_data32(uint32_t addr)
{
+ if(d_mem_stored == NULL) return 0xffffffff;
uint32_t val = read_debug_data16(addr) << 16;
val |= read_debug_data16(addr + 2);
return val;
#define ARG2 opram[2]
#define ARGW (opram[1]<<8) + opram[2]
-static unsigned Dasm680x (int subtype, _TCHAR *buf, unsigned pc, const UINT8 *oprom, const UINT8 *opram, symbol_t *first_symbol)
+unsigned MC6800::Dasm680x(int subtype, _TCHAR *buf, unsigned pc, const UINT8 *oprom, const UINT8 *opram, symbol_t *first_symbol)
{
// UINT32 flags = 0;
int invalid_mask;
int MC6800::debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len)
{
uint8_t ops[4];
- for(int i = 0; i < 4; i++) {
- int wait;
- ops[i] = d_mem_stored->read_data8w(pc + i, &wait);
+ if(d_mem_stored != NULL) {
+ for(int i = 0; i < 4; i++) {
+ int wait;
+ ops[i] = d_mem_stored->read_data8w(pc + i, &wait);
+ }
}
-#if defined(HAS_MC6800)
+//#if defined(HAS_MC6800)
return Dasm680x(6800, buffer, pc, ops, ops, d_debugger->first_symbol);
-#elif defined(HAS_MC6801)
- return Dasm680x(6801, buffer, pc, ops, ops, d_debugger->first_symbol);
-#elif defined(HAS_HD6301)
- return Dasm680x(6301, buffer, pc, ops, ops, d_debugger->first_symbol);
-#elif defined(HAS_MB8861)
- return Dasm680x(6800, buffer, pc, ops, ops, d_debugger->first_symbol); // FIXME
-#endif
+//#elif defined(HAS_MC6801)
+// return Dasm680x(6801, buffer, pc, ops, ops, d_debugger->first_symbol);
+//#elif defined(HAS_HD6301)
+// return Dasm680x(6301, buffer, pc, ops, ops, d_debugger->first_symbol);
+//#elif defined(HAS_MB8861)
+// return Dasm680x(6800, buffer, pc, ops, ops, d_debugger->first_symbol); // FIXME
+//#endif
return 0;
}
-#endif
+//#endif
void MC6800::enter_interrupt(uint16_t irq_vector)
{
case 0x01: nop(); break;
case 0x02: illegal(); break;
case 0x03: illegal(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0x04: lsrd(); break;
- case 0x05: asld(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0x04: lsrd(); break;
+// case 0x05: asld(); break;
+//#else
case 0x04: illegal(); break;
case 0x05: illegal(); break;
-#endif
+//#endif
case 0x06: tap(); break;
case 0x07: tpa(); break;
case 0x08: inx(); break;
case 0x0f: sei(); break;
case 0x10: sba(); break;
case 0x11: cba(); break;
-#if defined(HAS_HD6301)
- case 0x12: undoc1(); break;
- case 0x13: undoc2(); break;
-#else
+//#if defined(HAS_HD6301)
+// case 0x12: undoc1(); break;
+// case 0x13: undoc2(); break;
+//#else
case 0x12: illegal(); break;
case 0x13: illegal(); break;
-#endif
+//#endif
case 0x14: illegal(); break;
case 0x15: illegal(); break;
case 0x16: tab(); break;
case 0x17: tba(); break;
-#if defined(HAS_HD6301)
- case 0x18: xgdx(); break;
-#else
+//#if defined(HAS_HD6301)
+// case 0x18: xgdx(); break;
+//#else
case 0x18: illegal(); break;
-#endif
+//#endif
case 0x19: daa(); break;
-#if defined(HAS_HD6301)
- case 0x1a: slp(); break;
-#else
+//#if defined(HAS_HD6301)
+// case 0x1a: slp(); break;
+//#else
case 0x1a: illegal(); break;
-#endif
+//#endif
case 0x1b: aba(); break;
case 0x1c: illegal(); break;
case 0x1d: illegal(); break;
case 0x35: txs(); break;
case 0x36: psha(); break;
case 0x37: pshb(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0x38: pulx(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0x38: pulx(); break;
+//#else
case 0x38: illegal(); break;
-#endif
+//#endif
case 0x39: rts(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0x3a: abx(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0x3a: abx(); break;
+//#else
case 0x3a: illegal(); break;
-#endif
+//#endif
case 0x3b: rti(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0x3c: pshx(); break;
- case 0x3d: mul(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0x3c: pshx(); break;
+// case 0x3d: mul(); break;
+//#else
case 0x3c: illegal(); break;
case 0x3d: illegal(); break;
-#endif
+//#endif
case 0x3e: wai(); break;
case 0x3f: swi(); break;
case 0x40: nega(); break;
case 0x5e: illegal(); break;
case 0x5f: clrb(); break;
case 0x60: neg_ix(); break;
-#if defined(HAS_HD6301)
- case 0x61: aim_ix(); break;
- case 0x62: oim_ix(); break;
-#else
+//#if defined(HAS_HD6301)
+// case 0x61: aim_ix(); break;
+// case 0x62: oim_ix(); break;
+//#else
case 0x61: illegal(); break;
case 0x62: illegal(); break;
-#endif
+//#endif
case 0x63: com_ix(); break;
case 0x64: lsr_ix(); break;
-#if defined(HAS_HD6301)
- case 0x65: eim_ix(); break;
-#else
+//#if defined(HAS_HD6301)
+// case 0x65: eim_ix(); break;
+//#else
case 0x65: illegal(); break;
-#endif
+//#endif
case 0x66: ror_ix(); break;
case 0x67: asr_ix(); break;
case 0x68: asl_ix(); break;
case 0x69: rol_ix(); break;
case 0x6a: dec_ix(); break;
-#if defined(HAS_HD6301)
- case 0x6b: tim_ix(); break;
-#else
+//#if defined(HAS_HD6301)
+// case 0x6b: tim_ix(); break;
+//#else
case 0x6b: illegal(); break;
-#endif
+//#endif
case 0x6c: inc_ix(); break;
case 0x6d: tst_ix(); break;
case 0x6e: jmp_ix(); break;
case 0x6f: clr_ix(); break;
case 0x70: neg_ex(); break;
-#if defined(HAS_HD6301)
- case 0x71: aim_di(); break;
- case 0x72: oim_di(); break;
-#elif defined(HAS_MB8861)
- case 0x71: nim_ix(); break;
- case 0x72: oim_ix_mb8861(); break;
-#else
+//#if defined(HAS_HD6301)
+// case 0x71: aim_di(); break;
+// case 0x72: oim_di(); break;
+//#elif defined(HAS_MB8861)
+// case 0x71: nim_ix(); break;
+// case 0x72: oim_ix_mb8861(); break;
+//#else
case 0x71: illegal(); break;
case 0x72: illegal(); break;
-#endif
+//#endif
case 0x73: com_ex(); break;
case 0x74: lsr_ex(); break;
-#if defined(HAS_HD6301)
- case 0x75: eim_di(); break;
-#elif defined(HAS_MB8861)
- case 0x75: xim_ix(); break;
-#else
+//#if defined(HAS_HD6301)
+// case 0x75: eim_di(); break;
+//#elif defined(HAS_MB8861)
+// case 0x75: xim_ix(); break;
+//#else
case 0x75: illegal(); break;
-#endif
+//#endif
case 0x76: ror_ex(); break;
case 0x77: asr_ex(); break;
case 0x78: asl_ex(); break;
case 0x79: rol_ex(); break;
case 0x7a: dec_ex(); break;
-#if defined(HAS_HD6301)
- case 0x7b: tim_di(); break;
-#elif defined(HAS_MB8861)
- case 0x7b: tmm_ix(); break;
-#else
+//#if defined(HAS_HD6301)
+// case 0x7b: tim_di(); break;
+//#elif defined(HAS_MB8861)
+// case 0x7b: tmm_ix(); break;
+//#else
case 0x7b: illegal(); break;
-#endif
+//#endif
case 0x7c: inc_ex(); break;
case 0x7d: tst_ex(); break;
case 0x7e: jmp_ex(); break;
case 0x80: suba_im(); break;
case 0x81: cmpa_im(); break;
case 0x82: sbca_im(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0x83: subd_im(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0x83: subd_im(); break;
+//#else
case 0x83: illegal(); break;
-#endif
+//#endif
case 0x84: anda_im(); break;
case 0x85: bita_im(); break;
case 0x86: lda_im(); break;
case 0x89: adca_im(); break;
case 0x8a: ora_im(); break;
case 0x8b: adda_im(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0x8c: cpx_im (); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0x8c: cpx_im (); break;
+//#else
case 0x8c: cmpx_im(); break;
-#endif
+//#endif
case 0x8d: bsr(); break;
case 0x8e: lds_im(); break;
case 0x8f: sts_im(); break;
case 0x90: suba_di(); break;
case 0x91: cmpa_di(); break;
case 0x92: sbca_di(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0x93: subd_di(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0x93: subd_di(); break;
+//#else
case 0x93: illegal(); break;
-#endif
+//#endif
case 0x94: anda_di(); break;
case 0x95: bita_di(); break;
case 0x96: lda_di(); break;
case 0x99: adca_di(); break;
case 0x9a: ora_di(); break;
case 0x9b: adda_di(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0x9c: cpx_di (); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0x9c: cpx_di (); break;
+//#else
case 0x9c: cmpx_di(); break;
-#endif
+//#endif
case 0x9d: jsr_di(); break;
case 0x9e: lds_di(); break;
case 0x9f: sts_di(); break;
case 0xa0: suba_ix(); break;
case 0xa1: cmpa_ix(); break;
case 0xa2: sbca_ix(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0xa3: subd_ix(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0xa3: subd_ix(); break;
+//#else
case 0xa3: illegal(); break;
-#endif
+//#endif
case 0xa4: anda_ix(); break;
case 0xa5: bita_ix(); break;
case 0xa6: lda_ix(); break;
case 0xa9: adca_ix(); break;
case 0xaa: ora_ix(); break;
case 0xab: adda_ix(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0xac: cpx_ix (); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0xac: cpx_ix (); break;
+//#else
case 0xac: cmpx_ix(); break;
-#endif
+//#endif
case 0xad: jsr_ix(); break;
case 0xae: lds_ix(); break;
case 0xaf: sts_ix(); break;
case 0xb0: suba_ex(); break;
case 0xb1: cmpa_ex(); break;
case 0xb2: sbca_ex(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0xb3: subd_ex(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0xb3: subd_ex(); break;
+//#else
case 0xb3: illegal(); break;
-#endif
+//#endif
case 0xb4: anda_ex(); break;
case 0xb5: bita_ex(); break;
case 0xb6: lda_ex(); break;
case 0xb9: adca_ex(); break;
case 0xba: ora_ex(); break;
case 0xbb: adda_ex(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0xbc: cpx_ex (); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0xbc: cpx_ex (); break;
+//#else
case 0xbc: cmpx_ex(); break;
-#endif
+//#endif
case 0xbd: jsr_ex(); break;
case 0xbe: lds_ex(); break;
case 0xbf: sts_ex(); break;
case 0xc0: subb_im(); break;
case 0xc1: cmpb_im(); break;
case 0xc2: sbcb_im(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0xc3: addd_im(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0xc3: addd_im(); break;
+//#else
case 0xc3: illegal(); break;
-#endif
+//#endif
case 0xc4: andb_im(); break;
case 0xc5: bitb_im(); break;
case 0xc6: ldb_im(); break;
case 0xc9: adcb_im(); break;
case 0xca: orb_im(); break;
case 0xcb: addb_im(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0xcc: ldd_im(); break;
- case 0xcd: std_im(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0xcc: ldd_im(); break;
+// case 0xcd: std_im(); break;
+//#else
case 0xcc: illegal(); break;
case 0xcd: illegal(); break;
-#endif
+//#endif
case 0xce: ldx_im(); break;
case 0xcf: stx_im(); break;
case 0xd0: subb_di(); break;
case 0xd1: cmpb_di(); break;
case 0xd2: sbcb_di(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0xd3: addd_di(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0xd3: addd_di(); break;
+//#else
case 0xd3: illegal(); break;
-#endif
+//#endif
case 0xd4: andb_di(); break;
case 0xd5: bitb_di(); break;
case 0xd6: ldb_di(); break;
case 0xd9: adcb_di(); break;
case 0xda: orb_di(); break;
case 0xdb: addb_di(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0xdc: ldd_di(); break;
- case 0xdd: std_di(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0xdc: ldd_di(); break;
+// case 0xdd: std_di(); break;
+//#else
case 0xdc: illegal(); break;
case 0xdd: illegal(); break;
-#endif
+//#endif
case 0xde: ldx_di(); break;
case 0xdf: stx_di(); break;
case 0xe0: subb_ix(); break;
case 0xe1: cmpb_ix(); break;
case 0xe2: sbcb_ix(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0xe3: addd_ix(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0xe3: addd_ix(); break;
+//#else
case 0xe3: illegal(); break;
-#endif
+//#endif
case 0xe4: andb_ix(); break;
case 0xe5: bitb_ix(); break;
case 0xe6: ldb_ix(); break;
case 0xe9: adcb_ix(); break;
case 0xea: orb_ix(); break;
case 0xeb: addb_ix(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0xec: ldd_ix(); break;
- case 0xed: std_ix(); break;
-#elif defined(HAS_MB8861)
- case 0xec: adx_im(); break;
- case 0xed: illegal(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0xec: ldd_ix(); break;
+// case 0xed: std_ix(); break;
+//#elif defined(HAS_MB8861)
+// case 0xec: adx_im(); break;
+// case 0xed: illegal(); break;
+//#else
case 0xec: illegal(); break;
case 0xed: illegal(); break;
-#endif
+//#endif
case 0xee: ldx_ix(); break;
case 0xef: stx_ix(); break;
case 0xf0: subb_ex(); break;
case 0xf1: cmpb_ex(); break;
case 0xf2: sbcb_ex(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0xf3: addd_ex(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0xf3: addd_ex(); break;
+//#else
case 0xf3: illegal(); break;
-#endif
+//#endif
case 0xf4: andb_ex(); break;
case 0xf5: bitb_ex(); break;
case 0xf6: ldb_ex(); break;
case 0xf9: adcb_ex(); break;
case 0xfa: orb_ex(); break;
case 0xfb: addb_ex(); break;
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- case 0xfc: ldd_ex(); break;
- case 0xfd: std_ex(); break;
-#elif defined(HAS_MB8861)
- case 0xfc: adx_ex(); break;
- case 0xfd: illegal(); break;
-#else
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// case 0xfc: ldd_ex(); break;
+// case 0xfd: std_ex(); break;
+//#elif defined(HAS_MB8861)
+// case 0xfc: adx_ex(); break;
+// case 0xfd: illegal(); break;
+//#else
case 0xfc: illegal(); break;
case 0xfd: illegal(); break;
-#endif
+//#endif
case 0xfe: ldx_ex(); break;
case 0xff: stx_ex(); break;
#if defined(_MSC_VER) && (_MSC_VER >= 1200)
/* $00 ILLEGAL */
void MC6800::illegal()
{
-#ifdef HAS_HD6301
- TAKE_TRAP;
-#endif
+//#ifdef HAS_HD6301
+// TAKE_TRAP;
+//#endif
}
/* $01 NOP */
/* $03 ILLEGAL */
-/* $04 LSRD inherent -0*-* */
-void MC6800::lsrd()
-{
- uint16_t t;
- CLR_NZC;
- t = D;
- CC |= (t & 0x0001);
- t >>= 1;
- SET_Z16(t);
- D = t;
-}
-
-/* $05 ASLD inherent ?**** */
-void MC6800::asld()
-{
- int r;
- uint16_t t;
- t = D;
- r = t << 1;
- CLR_NZVC;
- SET_FLAGS16(t, t, r);
- D = r;
-}
/* $06 TAP inherent ##### */
void MC6800::tap()
SET_FLAGS8(A, B, t);
}
-/* $12 ILLEGAL */
-void MC6800::undoc1()
-{
- X += RM(S + 1);
-}
-
-/* $13 ILLEGAL */
-void MC6800::undoc2()
-{
- X += RM(S + 1);
-}
-
/* $14 ILLEGAL */
/* $15 ILLEGAL */
SET_NZ8(A);
}
-/* $18 XGDX inherent ----- */ /* HD6301 only */
-void MC6800::xgdx()
-{
- uint16_t t = X;
- X = D;
- D = t;
-}
/* $19 DAA inherent (A) -**0* */
void MC6800::daa()
/* $1a ILLEGAL */
-/* $1a SLP */ /* HD6301 only */
-void MC6800::slp()
-{
- /* wait for next IRQ (same as waiting of wai) */
- wai_state |= HD6301_SLP;
-}
/* $1b ABA inherent ***** */
void MC6800::aba()
PUSHBYTE(B);
}
-/* $38 PULX inherent ----- */
-void MC6800::pulx()
-{
- PULLWORD(pX);
-}
/* $39 RTS inherent ----- */
void MC6800::rts()
PULLWORD(pPC);
}
-/* $3a ABX inherent ----- */
-void MC6800::abx()
-{
- X += B;
-}
/* $3b RTI inherent ##### */
void MC6800::rti()
PULLWORD(pPC);
}
-/* $3c PSHX inherent ----- */
-void MC6800::pshx()
-{
- PUSHWORD(pX);
-}
-
-/* $3d MUL inherent --*-@ */
-void MC6800::mul()
-{
- uint16_t t;
- t = A*B;
- CLR_C;
- if(t & 0x80) SEC;
- D = t;
-}
/* $3e WAI inherent ----- */
void MC6800::wai()
WM(EAD, r);
}
-/* $61 AIM --**0- */ /* HD6301 only */
-void MC6800::aim_ix()
-{
- uint8_t t, r;
- IMMBYTE(t);
- IDXBYTE(r);
- r &= t;
- CLR_NZV;
- SET_NZ8(r);
- WM(EAD, r);
-}
-
-/* $62 OIM --**0- */ /* HD6301 only */
-void MC6800::oim_ix()
-{
- uint8_t t, r;
- IMMBYTE(t);
- IDXBYTE(r);
- r |= t;
- CLR_NZV;
- SET_NZ8(r);
- WM(EAD, r);
-}
/* $63 COM indexed -**01 */
void MC6800::com_ix()
WM(EAD, t);
}
-/* $65 EIM --**0- */ /* HD6301 only */
-void MC6800::eim_ix()
-{
- uint8_t t, r;
- IMMBYTE(t);
- IDXBYTE(r);
- r ^= t;
- CLR_NZV;
- SET_NZ8(r);
- WM(EAD, r);
-}
/* $66 ROR indexed -**-* */
void MC6800::ror_ix()
WM(EAD, t);
}
-/* $6b TIM --**0- */ /* HD6301 only */
-void MC6800::tim_ix()
-{
- uint8_t t, r;
- IMMBYTE(t);
- IDXBYTE(r);
- r &= t;
- CLR_NZV;
- SET_NZ8(r);
-}
/* $6c INC indexed -***- */
void MC6800::inc_ix()
WM(EAD, r);
}
-/* $71 AIM --**0- */ /* HD6301 only */
-void MC6800::aim_di()
-{
- uint8_t t, r;
- IMMBYTE(t);
- DIRBYTE(r);
- r &= t;
- CLR_NZV;
- SET_NZ8(r);
- WM(EAD, r);
-}
-
-/* $71 NIM --**0- */ /* MB8861 only */
-void MC6800::nim_ix()
-{
- uint8_t t, r;
- IMMBYTE(t);
- IDXBYTE(r);
- r &= t;
- CLR_NZV;
- if(!r) {
- SEZ;
- } else {
- SEN;
- }
- WM(EAD, r);
-}
-
-/* $72 OIM --**0- */ /* HD6301 only */
-void MC6800::oim_di()
-{
- uint8_t t, r;
- IMMBYTE(t);
- DIRBYTE(r);
- r |= t;
- CLR_NZV;
- SET_NZ8(r);
- WM(EAD, r);
-}
-/* $72 OIM --**0- */ /* MB8861 only */
-void MC6800::oim_ix_mb8861()
-{
- uint8_t t, r;
- IMMBYTE(t);
- IDXBYTE(r);
- r |= t;
- CLR_NZV;
- if(!r) {
- SEZ;
- } else {
- SEN;
- }
- WM(EAD, r);
-}
/* $73 COM extended -**01 */
void MC6800::com_ex()
WM(EAD, t);
}
-/* $75 EIM --**0- */ /* HD6301 only */
-void MC6800::eim_di()
-{
- uint8_t t, r;
- IMMBYTE(t);
- DIRBYTE(r);
- r ^= t;
- CLR_NZV;
- SET_NZ8(r);
- WM(EAD, r);
-}
-/* $75 XIM --**-- */ /* MB8861 only */
-void MC6800::xim_ix()
-{
- uint8_t t, r;
- IMMBYTE(t);
- IDXBYTE(r);
- r ^= t;
- CLR_NZ;
- if(!r) {
- SEZ;
- } else {
- SEN;
- }
- WM(EAD, r);
-}
/* $76 ROR extended -**-* */
void MC6800::ror_ex()
WM(EAD, t);
}
-/* $7b TIM --**0- */ /* HD6301 only */
-void MC6800::tim_di()
-{
- uint8_t t, r;
- IMMBYTE(t);
- DIRBYTE(r);
- r &= t;
- CLR_NZV;
- SET_NZ8(r);
-}
-/* $7b TMM --***- */ /* MB8861 only */
-void MC6800::tmm_ix()
-{
- uint8_t t, r;
- IMMBYTE(t);
- IDXBYTE(r);
- r &= t;
- CLR_NZV;
- if(!t || !r) {
- SEZ;
- } else if(r == t) {
- SEV;
- } else {
- SEN;
- }
-}
/* $7c INC extended -***- */
void MC6800::inc_ex()
A = (uint8_t)r;
}
-/* $83 SUBD immediate -**** */
-void MC6800::subd_im()
-{
- uint32_t r, d;
- pair_t b;
- IMMWORD(b);
- d = D;
- r = d - b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
- D = r;
-}
-
/* $84 ANDA immediate -**0- */
void MC6800::anda_im()
{
SET_V16(d, b.d, r);
}
-/* $8c CPX immediate -**** (6801) */
-void MC6800::cpx_im()
-{
- uint32_t r, d;
- pair_t b;
- IMMWORD(b);
- d = X;
- r = d - b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
-}
-
/* $8d BSR ----- */
void MC6800::bsr()
A = (uint8_t)r;
}
-/* $93 SUBD direct -**** */
-void MC6800::subd_di()
-{
- uint32_t r, d;
- pair_t b;
- DIRWORD(b);
- d = D;
- r = d - b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
- D = r;
-}
-
/* $94 ANDA direct -**0- */
void MC6800::anda_di()
{
SET_V16(d, b.d, r);
}
-/* $9c CPX direct -**** (6801) */
-void MC6800::cpx_di()
-{
- uint32_t r, d;
- pair_t b;
- DIRWORD(b);
- d = X;
- r = d - b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
-}
/* $9d JSR direct ----- */
void MC6800::jsr_di()
A = (uint8_t)r;
}
-/* $a3 SUBD indexed -**** */
-void MC6800::subd_ix()
-{
- uint32_t r, d;
- pair_t b;
- IDXWORD(b);
- d = D;
- r = d - b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
- D = r;
-}
/* $a4 ANDA indexed -**0- */
void MC6800::anda_ix()
SET_V16(d, b.d, r);
}
-/* $ac CPX indexed -**** (6801)*/
-void MC6800::cpx_ix()
-{
- uint32_t r, d;
- pair_t b;
- IDXWORD(b);
- d = X;
- r = d - b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
-}
/* $ad JSR indexed ----- */
void MC6800::jsr_ix()
A = (uint8_t)r;
}
-/* $b3 SUBD extended -**** */
-void MC6800::subd_ex()
-{
- uint32_t r, d;
- pair_t b;
- EXTWORD(b);
- d = D;
- r = d - b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
- D = r;
-}
/* $b4 ANDA extended -**0- */
void MC6800::anda_ex()
SET_V16(d, b.d, r);
}
-/* $bc CPX extended -**** (6801) */
-void MC6800::cpx_ex()
-{
- uint32_t r, d;
- pair_t b;
- EXTWORD(b);
- d = X;
- r = d - b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
-}
-
/* $bd JSR extended ----- */
void MC6800::jsr_ex()
{
B = (uint8_t)r;
}
-/* $c3 ADDD immediate -**** */
-void MC6800::addd_im()
-{
- uint32_t r, d;
- pair_t b;
- IMMWORD(b);
- d = D;
- r = d + b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
- D = r;
-}
/* $c4 ANDB immediate -**0- */
void MC6800::andb_im()
B = (uint8_t)r;
}
-/* $CC LDD immediate -**0- */
-void MC6800::ldd_im()
-{
- IMMWORD(pD);
- CLR_NZV;
- SET_NZ16(D);
-}
-
-/* is this a legal instruction? */
-/* $cd STD immediate -**0- */
-void MC6800::std_im()
-{
- IMM16;
- CLR_NZV;
- SET_NZ16(D);
- WM16(EAD, &pD);
-}
-
/* $ce LDX immediate -**0- */
void MC6800::ldx_im()
{
B = (uint8_t)r;
}
-/* $d3 ADDD direct -**** */
-void MC6800::addd_di()
-{
- uint32_t r, d;
- pair_t b;
- DIRWORD(b);
- d = D;
- r = d + b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
- D = r;
-}
/* $d4 ANDB direct -**0- */
void MC6800::andb_di()
B = (uint8_t)r;
}
-/* $dc LDD direct -**0- */
-void MC6800::ldd_di()
-{
- DIRWORD(pD);
- CLR_NZV;
- SET_NZ16(D);
-}
-
-/* $dd STD direct -**0- */
-void MC6800::std_di()
-{
- DIRECT;
- CLR_NZV;
- SET_NZ16(D);
- WM16(EAD, &pD);
-}
-
/* $de LDX direct -**0- */
void MC6800::ldx_di()
{
B = (uint8_t)r;
}
-/* $e3 ADDD indexed -**** */
-void MC6800::addd_ix()
-{
- uint32_t r, d;
- pair_t b;
- IDXWORD(b);
- d = D;
- r = d + b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
- D = r;
-}
/* $e4 ANDB indexed -**0- */
void MC6800::andb_ix()
B = (uint8_t)r;
}
-/* $ec LDD indexed -**0- */
-void MC6800::ldd_ix()
-{
- IDXWORD(pD);
- CLR_NZV;
- SET_NZ16(D);
-}
-/* $ec ADX immediate -**** */ /* MB8861 only */
-void MC6800::adx_im()
-{
- uint32_t r, d, t;
- IMMBYTE(t);
- d = X;
- r = d + t;
- CLR_NZVC;
- SET_FLAGS16(d, t, r);
- X = r;
-}
-/* $ed STD indexed -**0- */
-void MC6800::std_ix()
-{
- INDEXED;
- CLR_NZV;
- SET_NZ16(D);
- WM16(EAD, &pD);
-}
/* $ee LDX indexed -**0- */
void MC6800::ldx_ix()
B = (uint8_t)r;
}
-/* $f3 ADDD extended -**** */
-void MC6800::addd_ex()
-{
- uint32_t r, d;
- pair_t b;
- EXTWORD(b);
- d = D;
- r = d + b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
- D = r;
-}
/* $f4 ANDB extended -**0- */
void MC6800::andb_ex()
B = (uint8_t)r;
}
-/* $fc LDD extended -**0- */
-void MC6800::ldd_ex()
-{
- EXTWORD(pD);
- CLR_NZV;
- SET_NZ16(D);
-}
-
-/* $fc ADX immediate -**** */ /* MB8861 only */
-void MC6800::adx_ex()
-{
- uint32_t r, d;
- pair_t b;
- EXTWORD(b);
- d = X;
- r = d + b.d;
- CLR_NZVC;
- SET_FLAGS16(d, b.d, r);
- X = r;
-}
-/* $fd STD extended -**0- */
-void MC6800::std_ex()
-{
- EXTENDED;
- CLR_NZV;
- SET_NZ16(D);
- WM16(EAD, &pD);
-}
/* $fe LDX extended -**0- */
void MC6800::ldx_ex()
state_fio->FputInt32(wai_state);
state_fio->FputInt32(int_state);
state_fio->FputInt32(icount);
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- for(int i = 0; i < 4; i++) {
- state_fio->FputUint8(port[i].wreg);
- state_fio->FputUint8(port[i].rreg);
- state_fio->FputUint8(port[i].ddr);
- state_fio->FputUint8(port[i].latched_data);
- state_fio->FputBool(port[i].latched);
- state_fio->FputBool(port[i].first_write);
- }
- state_fio->FputUint8(p3csr);
- state_fio->FputBool(p3csr_is3_flag_read);
- state_fio->FputBool(sc1_state);
- state_fio->FputBool(sc2_state);
- state_fio->FputUint32(counter.d);
- state_fio->FputUint32(output_compare.d);
- state_fio->FputUint32(timer_over.d);
- state_fio->FputUint8(tcsr);
- state_fio->FputUint8(pending_tcsr);
- state_fio->FputUint16(input_capture);
-#ifdef HAS_HD6301
- state_fio->FputUint16(latch09);
-#endif
- state_fio->FputUint32(timer_next);
- recv_buffer->save_state((void *)state_fio);
- state_fio->FputUint8(trcsr);
- state_fio->FputUint8(rdr);
- state_fio->FputUint8(tdr);
- state_fio->FputBool(trcsr_read_tdre);
- state_fio->FputBool(trcsr_read_orfe);
- state_fio->FputBool(trcsr_read_rdrf);
- state_fio->FputUint8(rmcr);
- state_fio->FputInt32(sio_counter);
- state_fio->FputUint8(ram_ctrl);
- state_fio->Fwrite(ram, sizeof(ram), 1);
-#endif
}
bool MC6800::load_state(FILEIO* state_fio)
wai_state = state_fio->FgetInt32();
int_state = state_fio->FgetInt32();
icount = state_fio->FgetInt32();
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- for(int i = 0; i < 4; i++) {
- port[i].wreg = state_fio->FgetUint8();
- port[i].rreg = state_fio->FgetUint8();
- port[i].ddr = state_fio->FgetUint8();
- port[i].latched_data = state_fio->FgetUint8();
- port[i].latched = state_fio->FgetBool();
- port[i].first_write = state_fio->FgetBool();
- }
- p3csr = state_fio->FgetUint8();
- p3csr_is3_flag_read = state_fio->FgetBool();
- sc1_state = state_fio->FgetBool();
- sc2_state = state_fio->FgetBool();
- counter.d = state_fio->FgetUint32();
- output_compare.d = state_fio->FgetUint32();
- timer_over.d = state_fio->FgetUint32();
- tcsr = state_fio->FgetUint8();
- pending_tcsr = state_fio->FgetUint8();
- input_capture = state_fio->FgetUint16();
-#ifdef HAS_HD6301
- latch09 = state_fio->FgetUint16();
-#endif
- timer_next = state_fio->FgetUint32();
- if(!recv_buffer->load_state((void *)state_fio)) {
- return false;
- }
- trcsr = state_fio->FgetUint8();
- rdr = state_fio->FgetUint8();
- tdr = state_fio->FgetUint8();
- trcsr_read_tdre = state_fio->FgetBool();
- trcsr_read_orfe = state_fio->FgetBool();
- trcsr_read_rdrf = state_fio->FgetBool();
- rmcr = state_fio->FgetUint8();
- sio_counter = state_fio->FgetInt32();
- ram_ctrl = state_fio->FgetUint8();
- state_fio->Fread(ram, sizeof(ram), 1);
-#endif
return true;
}
#ifndef _MC6800_H_
#define _MC6800_H_
-#include "vm.h"
-#include "../emu.h"
+//#include "vm.h"
+//#include "../emu.h"
#include "device.h"
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
-#define SIG_MC6801_PORT_1 0
-#define SIG_MC6801_PORT_2 1
-#define SIG_MC6801_PORT_3 2
-#define SIG_MC6801_PORT_4 3
-#define SIG_MC6801_PORT_3_SC1 4
-#define SIG_MC6801_PORT_3_SC2 5
-#define SIG_MC6801_SIO_RECV 6
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+//#define SIG_MC6801_PORT_1 0
+//#define SIG_MC6801_PORT_2 1
+//#define SIG_MC6801_PORT_3 2
+//#define SIG_MC6801_PORT_4 3
+//#define SIG_MC6801_PORT_3_SC1 4
+//#define SIG_MC6801_PORT_3_SC2 5
+//#define SIG_MC6801_SIO_RECV 6
-class FIFO;
-#endif
+//class FIFO;
+//#endif
-#ifdef USE_DEBUGGER
+//#ifdef USE_DEBUGGER
class DEBUGGER;
-#endif
+//#endif
class MC6800 : public DEVICE
{
private:
+
+protected:
DEVICE *d_mem;
-#ifdef USE_DEBUGGER
+//#ifdef USE_DEBUGGER
DEBUGGER *d_debugger;
DEVICE *d_mem_stored;
-#endif
+//#endif
+ static const uint8_t flags8i[256];
+ static const uint8_t flags8d[256];
+#define XX 5 // invalid opcode unknown cc
+ const uint8_t cycles[256] = {
+//#if defined(HAS_MC6800)
+ XX, 2,XX,XX,XX,XX, 2, 2, 4, 4, 2, 2, 2, 2, 2, 2,
+ 2, 2,XX,XX,XX,XX, 2, 2,XX, 2,XX, 2,XX,XX,XX,XX,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4,XX, 5,XX,10,XX,XX, 9,12,
+ 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
+ 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
+ 7,XX,XX, 7, 7,XX, 7, 7, 7, 7, 7,XX, 7, 7, 4, 7,
+ 6,XX,XX, 6, 6,XX, 6, 6, 6, 6, 6,XX, 6, 6, 3, 6,
+ 2, 2, 2,XX, 2, 2, 2, 3, 2, 2, 2, 2, 3, 8, 3, 4,
+ 3, 3, 3,XX, 3, 3, 3, 4, 3, 3, 3, 3, 4, 6, 4, 5,
+ 5, 5, 5,XX, 5, 5, 5, 6, 5, 5, 5, 5, 6, 8, 6, 7,
+ 4, 4, 4,XX, 4, 4, 4, 5, 4, 4, 4, 4, 5, 9, 5, 6,
+ 2, 2, 2,XX, 2, 2, 2, 3, 2, 2, 2, 2,XX,XX, 3, 4,
+ 3, 3, 3,XX, 3, 3, 3, 4, 3, 3, 3, 3,XX,XX, 4, 5,
+ 5, 5, 5,XX, 5, 5, 5, 6, 5, 5, 5, 5,XX,XX, 6, 7,
+ 4, 4, 4,XX, 4, 4, 4, 5, 4, 4, 4, 4,XX,XX, 5, 6
+ };
+#undef XX // invalid opcode unknown cc
pair_t pc;
uint16_t prevpc;
int icount;
- uint32_t RM(uint32_t Addr);
- void WM(uint32_t Addr, uint32_t Value);
+ virtual uint32_t RM(uint32_t Addr);
+ virtual void WM(uint32_t Addr, uint32_t Value);
uint32_t RM16(uint32_t Addr);
void WM16(uint32_t Addr, pair_t *p);
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- // data
- struct {
- uint8_t wreg;
- uint8_t rreg;
- uint8_t ddr;
- uint8_t latched_data;
- bool latched;
- // output signals
- outputs_t outputs;
- bool first_write;
- } port[4];
-
- uint8_t p3csr;
- bool p3csr_is3_flag_read;
- bool sc1_state;
- bool sc2_state;
- // timer
- pair_t counter;
- pair_t output_compare;
- pair_t timer_over;
- uint8_t tcsr;
- uint8_t pending_tcsr;
- uint16_t input_capture;
-#ifdef HAS_HD6301
- uint16_t latch09;
-#endif
- uint32_t timer_next;
-
- // serial i/o
- outputs_t outputs_sio;
- FIFO *recv_buffer;
- uint8_t trcsr, rdr, tdr;
- bool trcsr_read_tdre, trcsr_read_orfe, trcsr_read_rdrf;
- uint8_t rmcr;
- int sio_counter;
-
- // memory controller
- uint8_t ram_ctrl;
- uint8_t ram[128];
-
- uint32_t mc6801_io_r(uint32_t offset);
- void mc6801_io_w(uint32_t offset, uint32_t data);
- void increment_counter(int amount);
-#endif
-
- void run_one_opecode();
+ virtual void run_one_opecode();
void enter_interrupt(uint16_t irq_vector);
- void insn(uint8_t code);
+ virtual void insn(uint8_t code);
void aba();
- void abx();
void adca_di();
void adca_ex();
void adca_im();
void addb_ex();
void addb_im();
void addb_ix();
- void addd_di();
- void addd_ex();
- void addd_im();
- void addd_ix();
- void adx_ex();
- void adx_im();
- void aim_di();
- void aim_ix();
- void nim_ix();
+
void anda_di();
void anda_ex();
void anda_im();
void asl_ix();
void asla();
void aslb();
- void asld();
+
void asr_ex();
void asr_ix();
void asra();
void decb();
void des();
void dex();
- void eim_di();
- void eim_ix();
- void xim_ix();
+
void eora_di();
void eora_ex();
void eora_im();
void eorb_ex();
void eorb_im();
void eorb_ix();
- void illegal();
+ virtual void illegal();
void inc_ex();
void inc_ix();
void inca();
void ldb_ex();
void ldb_im();
void ldb_ix();
- void ldd_di();
- void ldd_ex();
- void ldd_im();
- void ldd_ix();
void lds_di();
void lds_ex();
void lds_im();
void lsr_ix();
void lsra();
void lsrb();
- void lsrd();
- void mul();
void neg_ex();
void neg_ix();
void nega();
void negb();
void nop();
- void oim_di();
- void oim_ix();
- void oim_ix_mb8861();
+
void ora_di();
void ora_ex();
void ora_im();
void orb_ix();
void psha();
void pshb();
- void pshx();
void pula();
void pulb();
- void pulx();
void rol_ex();
void rol_ix();
void rola();
void sec();
void sei();
void sev();
- void slp();
void sta_di();
void sta_ex();
void sta_im();
void stb_ex();
void stb_im();
void stb_ix();
- void std_di();
- void std_ex();
- void std_im();
- void std_ix();
void sts_di();
void sts_ex();
void sts_im();
void subb_ex();
void subb_im();
void subb_ix();
- void subd_di();
- void subd_ex();
- void subd_im();
- void subd_ix();
void swi();
void tab();
void tap();
void tba();
- void tim_di();
- void tim_ix();
- void tmm_ix();
+
void tpa();
void tst_ex();
void tst_ix();
void tstb();
void tsx();
void txs();
- void undoc1();
- void undoc2();
void wai();
- void xgdx();
- void cpx_di();
- void cpx_ex();
- void cpx_im();
- void cpx_ix();
-
+ unsigned Dasm680x(int subtype, _TCHAR *buf, unsigned pc, const UINT8 *oprom, const UINT8 *opram, symbol_t *first_symbol);
+
+ bool __USE_DEBUGGER;
public:
MC6800(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
{
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- for(int i = 0; i < 4; i++) {
- initialize_output_signals(&port[i].outputs);
- port[i].wreg = port[i].rreg = 0;//0xff;
- }
- initialize_output_signals(&outputs_sio);
-#endif
-#if defined(HAS_MC6801)
- set_device_name(_T("MC6801 MPU"));
-#elif defined(HAS_HD6301)
- set_device_name(_T("HD6301 MPU"));
-#else
+ d_mem = NULL;
+ d_debugger = NULL;
+ d_mem_stored = NULL;
+ __USE_DEBUGGER = false;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+// for(int i = 0; i < 4; i++) {
+// initialize_output_signals(&port[i].outputs);
+// port[i].wreg = port[i].rreg = 0;//0xff;
+// }
+// initialize_output_signals(&outputs_sio);
+//#endif
+//#if defined(HAS_MC6801)
+// set_device_name(_T("MC6801 MPU"));
+//#elif defined(HAS_HD6301)
+// set_device_name(_T("HD6301 MPU"));
+//#else
set_device_name(_T("MC6800 MPU"));
-#endif
-#if defined(HAS_MC6801)
- set_device_name(_T("MC6801 MPU"));
-#elif defined(HAS_HD6301)
- set_device_name(_T("HD6301 MPU"));
-#else
- set_device_name(_T("MC6800 MPU"));
-#endif
+//#endif
}
~MC6800() {}
// common functions
- void initialize();
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- void release();
-#endif
- void reset();
- int run(int clock);
- void write_signal(int id, uint32_t data, uint32_t mask);
+ virtual void initialize();
+ virtual void reset();
+ virtual int run(int clock);
+
+ virtual void write_signal(int id, uint32_t data, uint32_t mask);
uint32_t get_pc()
{
return prevpc;
{
return pc.w.l;
}
-#ifdef USE_DEBUGGER
+//#ifdef USE_DEBUGGER
void *get_debugger()
{
return d_debugger;
uint32_t read_debug_data32(uint32_t addr);
bool write_debug_reg(const _TCHAR *reg, uint32_t data);
void get_debug_regs_info(_TCHAR *buffer, size_t buffer_len);
- int debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len);
-#endif
- void save_state(FILEIO* state_fio);
- bool load_state(FILEIO* state_fio);
+ virtual int debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len);
+//#endif
+ virtual void save_state(FILEIO* state_fio);
+ virtual bool load_state(FILEIO* state_fio);
// unique functions
void set_context_mem(DEVICE* device)
{
d_mem = device;
}
-#ifdef USE_DEBUGGER
+//#ifdef USE_DEBUGGER
void set_context_debugger(DEBUGGER* device)
{
d_debugger = device;
}
-#endif
-#if defined(HAS_MC6801) || defined(HAS_HD6301)
- void set_context_port1(DEVICE* device, int id, uint32_t mask, int shift)
- {
- register_output_signal(&port[0].outputs, device, id, mask, shift);
- }
- void set_context_port2(DEVICE* device, int id, uint32_t mask, int shift)
- {
- register_output_signal(&port[1].outputs, device, id, mask, shift);
- }
- void set_context_port3(DEVICE* device, int id, uint32_t mask, int shift)
- {
- register_output_signal(&port[2].outputs, device, id, mask, shift);
- }
- void set_context_port4(DEVICE* device, int id, uint32_t mask, int shift)
- {
- register_output_signal(&port[2].outputs, device, id, mask, shift);
- }
- void set_context_sio(DEVICE* device, int id)
- {
- register_output_signal(&outputs_sio, device, id, 0xff);
- }
-#endif
+//#endif
};
#endif
--- /dev/null
+
+#ifndef __MC6800_CONSTS_H_
+#define __MC6800_CONSTS_H_
+
+#define INT_REQ_BIT 1
+#define NMI_REQ_BIT 2
+
+#define MC6800_WAI 8
+#define HD6301_SLP 0x10
+
+#define pPC pc
+#define pS sp
+#define pX ix
+#define pD acc_d
+#define pEA ea
+
+#define PC pc.w.l
+#define PCD pc.d
+#define S sp.w.l
+#define SD sp.d
+#define X ix.w.l
+#define D acc_d.w.l
+#define A acc_d.b.h
+#define B acc_d.b.l
+#define CC cc
+
+#define EAD ea.d
+#define EA ea.w.l
+
+//#define M_RDOP(Addr) d_mem->read_data8(Addr)
+//#define M_RDOP_ARG(Addr) d_mem->read_data8(Addr)
+#define M_RDOP(Addr) RM(Addr)
+#define M_RDOP_ARG(Addr) RM(Addr)
+
+/* macros to access memory */
+#define IMMBYTE(b) b = M_RDOP_ARG(PCD); PC++
+#define IMMWORD(w) w.b.h = M_RDOP_ARG(PCD); w.b.l = M_RDOP_ARG((PCD + 1) & 0xffff); PC += 2
+
+#define PUSHBYTE(b) WM(SD, b); --S
+#define PUSHWORD(w) WM(SD, w.b.l); --S; WM(SD, w.b.h); --S
+#define PULLBYTE(b) S++; b = RM(SD)
+#define PULLWORD(w) S++; w.b.h = RM(SD); S++; w.b.l = RM(SD)
+
+#define CLR_HNZVC CC &= 0xd0
+#define CLR_NZV CC &= 0xf1
+#define CLR_HNZC CC &= 0xd2
+#define CLR_NZVC CC &= 0xf0
+#define CLR_NZ CC &= 0xf3
+#define CLR_Z CC &= 0xfb
+#define CLR_NZC CC &= 0xf2
+#define CLR_ZC CC &= 0xfa
+#define CLR_C CC &= 0xfe
+
+#define SET_Z(a) if(!(a)) SEZ
+#define SET_Z8(a) SET_Z((uint8_t)(a))
+#define SET_Z16(a) SET_Z((uint16_t)(a))
+#define SET_N8(a) CC |= (((a) & 0x80) >> 4)
+#define SET_N16(a) CC |= (((a) & 0x8000) >> 12)
+#define SET_H(a,b,r) CC |= ((((a) ^ (b) ^ (r)) & 0x10) << 1)
+#define SET_C8(a) CC |= (((a) & 0x100) >> 8)
+#define SET_C16(a) CC |= (((a) & 0x10000) >> 16)
+#define SET_V8(a,b,r) CC |= ((((a) ^ (b) ^ (r) ^ ((r) >> 1)) & 0x80) >> 6)
+#define SET_V16(a,b,r) CC |= ((((a) ^ (b) ^ (r) ^ ((r) >> 1)) & 0x8000) >> 14)
+
+#define SET_FLAGS8I(a) {CC |= flags8i[(a) & 0xff];}
+#define SET_FLAGS8D(a) {CC |= flags8d[(a) & 0xff];}
+
+/* combos */
+#define SET_NZ8(a) {SET_N8(a); SET_Z8(a);}
+#define SET_NZ16(a) {SET_N16(a); SET_Z16(a);}
+#define SET_FLAGS8(a,b,r) {SET_N8(r); SET_Z8(r); SET_V8(a,b,r); SET_C8(r); }
+#define SET_FLAGS16(a,b,r) {SET_N16(r); SET_Z16(r); SET_V16(a,b,r); SET_C16(r);}
+
+/* for treating an uint8_t as a signed int16_t */
+#define SIGNED(b) ((int16_t)(b & 0x80 ? b | 0xff00 : b))
+
+/* Macros for addressing modes */
+#define DIRECT IMMBYTE(EAD)
+#define IMM8 EA = PC++
+#define IMM16 {EA = PC; PC += 2;}
+#define EXTENDED IMMWORD(pEA)
+#define INDEXED {EA = X + (uint8_t)M_RDOP_ARG(PCD); PC++;}
+
+/* macros to set status flags */
+#define SEC CC |= 0x01
+#define CLC CC &= 0xfe
+#define SEZ CC |= 0x04
+#define CLZ CC &= 0xfb
+#define SEN CC |= 0x08
+#define CLN CC &= 0xf7
+#define SEV CC |= 0x02
+#define CLV CC &= 0xfd
+#define SEH CC |= 0x20
+#define CLH CC &= 0xdf
+#define SEI CC |= 0x10
+#define CLI CC &= ~0x10
+
+/* macros for convenience */
+#define DIRBYTE(b) {DIRECT; b = RM(EAD); }
+#define DIRWORD(w) {DIRECT; w.d = RM16(EAD);}
+#define EXTBYTE(b) {EXTENDED; b = RM(EAD); }
+#define EXTWORD(w) {EXTENDED; w.d = RM16(EAD);}
+
+#define IDXBYTE(b) {INDEXED; b = RM(EAD); }
+#define IDXWORD(w) {INDEXED; w.d = RM16(EAD);}
+
+/* Macros for branch instructions */
+#define BRANCH(f) {IMMBYTE(t); if(f) {PC += SIGNED(t);}}
+#define NXORV ((CC & 0x08) ^ ((CC & 0x02) << 2))
+
+/* Note: don't use 0 cycles here for invalid opcodes so that we don't */
+/* hang in an infinite loop if we hit one */
+
+#endif /* __MC6800_CONSTS_H_ */
--- /dev/null
+/*
+ Skelton for retropc emulator
+
+ Origin : MAME 0.142
+ Author : Takeda.Toshiya
+ Date : 2011.04.23-
+
+ [ MC6801 ]
+*/
+#if defined(_MSC_VER) && (_MSC_VER >= 1400)
+#pragma warning( disable : 4996 )
+#endif
+
+#include "mc6801.h"
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+#include "../fifo.h"
+//#endif
+//#ifdef USE_DEBUGGER
+#include "debugger.h"
+#include "mc6800_consts.h"
+#include "mc6801_consts.h"
+//#endif
+/****************************************************************************/
+/* memory */
+/****************************************************************************/
+
+uint32_t MC6801::RM(uint32_t Addr)
+{
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ if(Addr < 0x20) {
+ return mc6801_io_r(Addr);
+ } else if(Addr >= 0x80 && Addr < 0x100 && (ram_ctrl & 0x40)) {
+ return ram[Addr & 0x7f];
+ }
+//#endif
+ return d_mem->read_data8(Addr);
+}
+
+void MC6801::WM(uint32_t Addr, uint32_t Value)
+{
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ if(Addr < 0x20) {
+ mc6801_io_w(Addr, Value);
+ } else if(Addr >= 0x80 && Addr < 0x100 && (ram_ctrl & 0x40)) {
+ ram[Addr & 0x7f] = Value;
+ } else
+//#endif
+ d_mem->write_data8(Addr, Value);
+}
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+
+uint32_t MC6801::mc6801_io_r(uint32_t offset)
+{
+ switch (offset) {
+ case 0x00:
+ // port1 data direction register
+ return port[0].ddr;
+ case 0x01:
+ // port2 data direction register
+ return port[1].ddr;
+ case 0x02:
+ // port1 data register
+ return (port[0].rreg & ~port[0].ddr) | (port[0].wreg & port[0].ddr);
+ case 0x03:
+ // port2 data register
+ return (port[1].rreg & ~port[1].ddr) | (port[1].wreg & port[1].ddr);
+ case 0x04:
+ // port3 data direction register (write only???)
+ return port[2].ddr;
+ case 0x05:
+ // port4 data direction register
+ return port[3].ddr;
+ case 0x06:
+ // port3 data register
+ if(p3csr_is3_flag_read) {
+ p3csr_is3_flag_read = false;
+ p3csr &= ~P3CSR_IS3_FLAG;
+ }
+ if(port[2].latched) {
+ port[2].latched = false;
+ return (port[2].latched_data & ~port[2].ddr) | (port[2].wreg & port[2].ddr);
+ }
+ return (port[2].rreg & ~port[2].ddr) | (port[2].wreg & port[2].ddr);
+ case 0x07:
+ // port4 data register
+ return (port[3].rreg & ~port[3].ddr) | (port[3].wreg & port[3].ddr);
+ case 0x08:
+ // timer control register
+ pending_tcsr = 0;
+ return tcsr;
+ case 0x09:
+ // free running counter (msb)
+ if(!(pending_tcsr & TCSR_TOF)) {
+ tcsr &= ~TCSR_TOF;
+ }
+ return counter.b.h;
+ case 0x0a:
+ // free running counter (lsb)
+ return counter.b.l;
+ case 0x0b:
+ // output compare register (msb)
+ if(!(pending_tcsr & TCSR_OCF)) {
+ tcsr &= ~TCSR_OCF;
+ }
+ return output_compare.b.h;
+ case 0x0c:
+ // output compare register (lsb)
+ if(!(pending_tcsr & TCSR_OCF)) {
+ tcsr &= ~TCSR_OCF;
+ }
+ return output_compare.b.l;
+ case 0x0d:
+ // input capture register (msb)
+ if(!(pending_tcsr & TCSR_ICF)) {
+ tcsr &= ~TCSR_ICF;
+ }
+ return (input_capture >> 0) & 0xff;
+ case 0x0e:
+ // input capture register (lsb)
+ return (input_capture >> 8) & 0xff;
+ case 0x0f:
+ // port3 control/status register
+ p3csr_is3_flag_read = true;
+ return p3csr;
+ case 0x10:
+ // rate and mode control register
+ return rmcr;
+ case 0x11:
+ if(trcsr & TRCSR_TDRE) {
+ trcsr_read_tdre = true;
+ }
+ if(trcsr & TRCSR_ORFE) {
+ trcsr_read_orfe = true;
+ }
+ if(trcsr & TRCSR_RDRF) {
+ trcsr_read_rdrf = true;
+ }
+ return trcsr;
+ case 0x12:
+ // receive data register
+ if(trcsr_read_orfe) {
+ trcsr_read_orfe = false;
+ trcsr &= ~TRCSR_ORFE;
+ }
+ if(trcsr_read_rdrf) {
+ trcsr_read_rdrf = false;
+ trcsr &= ~TRCSR_RDRF;
+ }
+ return rdr;
+ case 0x13:
+ // transmit data register
+ return tdr;
+ case 0x14:
+ // ram control register
+ return (ram_ctrl & 0x40) | 0x3f;
+ }
+ return 0;
+}
+
+void MC6801::mc6801_io_w(uint32_t offset, uint32_t data)
+{
+ switch(offset) {
+ case 0x00:
+ // port1 data direction register
+ port[0].ddr = data;
+ break;
+ case 0x01:
+ // port2 data direction register
+ port[1].ddr = data;
+ break;
+ case 0x02:
+ // port1 data register
+ if(port[0].wreg != data || port[0].first_write) {
+ write_signals(&port[0].outputs, data);
+ port[0].wreg = data;
+ port[0].first_write = false;
+ }
+ break;
+ case 0x03:
+ // port2 data register
+ if(port[1].wreg != data || port[1].first_write) {
+ write_signals(&port[1].outputs, data);
+ port[1].wreg = data;
+ port[1].first_write = false;
+ }
+ break;
+ case 0x04:
+ // port3 data direction register
+ port[2].ddr = data;
+ break;
+ case 0x05:
+ // port4 data direction register
+ port[3].ddr = data;
+ break;
+ case 0x06:
+ // port3 data register
+ if(p3csr_is3_flag_read) {
+ p3csr_is3_flag_read = false;
+ p3csr &= ~P3CSR_IS3_FLAG;
+ }
+ if(port[2].wreg != data || port[2].first_write) {
+ write_signals(&port[2].outputs, data);
+ port[2].wreg = data;
+ port[2].first_write = false;
+ }
+ break;
+ case 0x07:
+ // port4 data register
+ if(port[3].wreg != data || port[3].first_write) {
+ write_signals(&port[3].outputs, data);
+ port[3].wreg = data;
+ port[3].first_write = false;
+ }
+ break;
+ case 0x08:
+ // timer control/status register
+ tcsr = data;
+ pending_tcsr &= tcsr;
+ break;
+ case 0x09:
+ // free running counter (msb)
+//#ifdef HAS_HD6301
+// latch09 = data & 0xff;
+//#endif
+ CT = 0xfff8;
+ TOH = CTH;
+ MODIFIED_counters;
+ break;
+//#ifdef HAS_HD6301
+// case 0x0a:
+// // free running counter (lsb)
+// CT = (latch09 << 8) | (data & 0xff);
+// TOH = CTH;
+// MODIFIED_counters;
+/// break;
+//#endif
+ case 0x0b:
+ // output compare register (msb)
+ if(output_compare.b.h != data) {
+ output_compare.b.h = data;
+ MODIFIED_counters;
+ }
+ tcsr &=~TCSR_OCF;
+ break;
+ case 0x0c:
+ // output compare register (lsb)
+ if(output_compare.b.l != data) {
+ output_compare.b.l = data;
+ MODIFIED_counters;
+ }
+ tcsr &=~TCSR_OCF;
+ break;
+ case 0x0f:
+ // port3 control/status register
+ p3csr = (p3csr & P3CSR_IS3_FLAG) | (data & ~P3CSR_IS3_FLAG);
+ break;
+ case 0x10:
+ // rate and mode control register
+ rmcr = data;
+ break;
+ case 0x11:
+ // transmit/receive control/status register
+ trcsr = (trcsr & 0xe0) | (data & 0x1f);
+ break;
+ case 0x13:
+ // transmit data register
+ if(trcsr_read_tdre) {
+ trcsr_read_tdre = false;
+ trcsr &= ~TRCSR_TDRE;
+ }
+ tdr = data;
+ break;
+ case 0x14:
+ // ram control register
+ ram_ctrl = data;
+ break;
+ }
+}
+
+void MC6801::increment_counter(int amount)
+{
+ icount -= amount;
+
+ // timer
+ if((CTD += amount) >= timer_next) {
+ /* OCI */
+ if( CTD >= OCD) {
+ OCH++; // next IRQ point
+ tcsr |= TCSR_OCF;
+ pending_tcsr |= TCSR_OCF;
+ }
+ /* TOI */
+ if( CTD >= TOD) {
+ TOH++; // next IRQ point
+ tcsr |= TCSR_TOF;
+ pending_tcsr |= TCSR_TOF;
+ }
+ /* set next event */
+ SET_TIMER_EVENT;
+ }
+
+ // serial i/o
+ if((sio_counter -= amount) <= 0) {
+ if((trcsr & TRCSR_TE) && !(trcsr & TRCSR_TDRE)) {
+ write_signals(&outputs_sio, tdr);
+ trcsr |= TRCSR_TDRE;
+ }
+ if((trcsr & TRCSR_RE) && !recv_buffer->empty()) {
+ if(trcsr & TRCSR_WU) {
+ // skip 10 bits
+ trcsr &= ~TRCSR_WU;
+ recv_buffer->read();
+ } else if(!(trcsr & TRCSR_RDRF)) {
+ // note: wait reveived data is read by cpu, so overrun framing error never occurs
+ rdr = recv_buffer->read();
+ trcsr |= TRCSR_RDRF;
+ }
+ }
+ sio_counter += RMCR_SS[rmcr & 3];
+ }
+}
+//#else
+
+
+void MC6801::initialize()
+{
+ MC6800::initialize();
+
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ recv_buffer = new FIFO(0x10000);
+ ram_ctrl = 0xc0;
+//#endif
+//#ifdef USE_DEBUGGER
+ if(__USE_DEBUGGER) {
+ d_mem_stored = d_mem;
+ d_debugger->set_context_mem(d_mem);
+ }
+//#endif
+}
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+void MC6801::release()
+{
+ recv_buffer->release();
+ delete recv_buffer;
+}
+//#endif
+
+void MC6801::reset()
+{
+ CC = 0xc0;
+ SEI; /* IRQ disabled */
+ PCD = RM16(0xfffe);
+ S = X = D = EA = 0;
+
+ wai_state = 0;
+ int_state = 0;
+
+ icount = 0;
+
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ for(int i = 0; i < 4; i++) {
+ port[i].ddr = 0x00;
+ port[i].first_write = true;
+ port[i].latched = false;
+ }
+ p3csr = 0x00;
+ p3csr_is3_flag_read = false;
+ sc1_state = sc2_state = false;
+
+ tcsr = pending_tcsr = 0x00;
+ CTD = 0x0000;
+ OCD = 0xffff;
+ TOD = 0xffff;
+
+ recv_buffer->clear();
+ trcsr = TRCSR_TDRE;
+ trcsr_read_tdre = trcsr_read_orfe = trcsr_read_rdrf = false;
+ rmcr = 0x00;
+ sio_counter = RMCR_SS[rmcr & 3];
+
+ ram_ctrl |= 0x40;
+//#endif
+}
+
+void MC6801::write_signal(int id, uint32_t data, uint32_t mask)
+{
+ switch(id) {
+ case SIG_CPU_IRQ:
+ if(data & mask) {
+ int_state |= INT_REQ_BIT;
+ } else {
+ int_state &= ~INT_REQ_BIT;
+ }
+ break;
+ case SIG_CPU_NMI:
+ if(data & mask) {
+ int_state |= NMI_REQ_BIT;
+ } else {
+ int_state &= ~NMI_REQ_BIT;
+ }
+ break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case SIG_MC6801_PORT_1:
+ port[0].rreg = (port[0].rreg & ~mask) | (data & mask);
+ break;
+ case SIG_MC6801_PORT_2:
+ if((mask & 1) && (port[1].rreg & 1) != (data & 1) && (tcsr & 2) == ((data << 1) & 2)) {
+ // active TIN edge in
+ tcsr |= TCSR_ICF;
+ pending_tcsr |= TCSR_ICF;
+ input_capture = CT;
+ }
+ port[1].rreg = (port[1].rreg & ~mask) | (data & mask);
+ break;
+ case SIG_MC6801_PORT_3:
+ port[2].rreg = (port[2].rreg & ~mask) | (data & mask);
+ break;
+ case SIG_MC6801_PORT_4:
+ port[3].rreg = (port[3].rreg & ~mask) | (data & mask);
+ break;
+ case SIG_MC6801_PORT_3_SC1:
+ if(sc1_state && !(data & mask)) {
+ // SC1: H -> L
+ if(!port[2].latched && (p3csr & P3CSR_LE)) {
+ port[2].latched_data = port[2].rreg;
+ port[2].latched = true;
+ p3csr |= P3CSR_IS3_FLAG;
+ }
+ }
+ sc1_state = ((data & mask) != 0);
+ break;
+ case SIG_MC6801_PORT_3_SC2:
+ sc2_state = ((data & mask) != 0);
+ break;
+ case SIG_MC6801_SIO_RECV:
+ recv_buffer->write(data & mask);
+ break;
+//#endif
+ }
+}
+
+int MC6801::run(int clock)
+{
+ // run cpu
+ if(clock == -1) {
+ // run only one opcode
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ CLEANUP_COUNTERS();
+//#endif
+ icount = 0;
+ if(__USE_DEBUGGER) {
+//#ifdef USE_DEBUGGER
+ bool now_debugging = d_debugger->now_debugging;
+ if(now_debugging) {
+ d_debugger->check_break_points(PC);
+ if(d_debugger->now_suspended) {
+ emu->mute_sound();
+ while(d_debugger->now_debugging && d_debugger->now_suspended) {
+ emu->sleep(10);
+ }
+ }
+ if(d_debugger->now_debugging) {
+ d_mem = d_debugger;
+ } else {
+ now_debugging = false;
+ }
+
+ run_one_opecode();
+
+ if(now_debugging) {
+ if(!d_debugger->now_going) {
+ d_debugger->now_suspended = true;
+ }
+ d_mem = d_mem_stored;
+ }
+ } else {
+//#endif
+ run_one_opecode();
+ }
+ } else {
+ run_one_opecode();
+//#ifdef USE_DEBUGGER
+ }
+//#endif
+ return -icount;
+ } else {
+ /* run cpu while given clocks */
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ CLEANUP_COUNTERS();
+//#endif
+ icount += clock;
+ int first_icount = icount;
+
+ while(icount > 0) {
+//#ifdef USE_DEBUGGER
+ if(__USE_DEBUGGER) {
+ bool now_debugging = d_debugger->now_debugging;
+ if(now_debugging) {
+ d_debugger->check_break_points(PC);
+ if(d_debugger->now_suspended) {
+ emu->mute_sound();
+ while(d_debugger->now_debugging && d_debugger->now_suspended) {
+ emu->sleep(10);
+ }
+ }
+ if(d_debugger->now_debugging) {
+ d_mem = d_debugger;
+ } else {
+ now_debugging = false;
+ }
+
+ run_one_opecode();
+
+ if(now_debugging) {
+ if(!d_debugger->now_going) {
+ d_debugger->now_suspended = true;
+ }
+ d_mem = d_mem_stored;
+ }
+ } else {
+//#endif
+ run_one_opecode();
+//#ifdef USE_DEBUGGER
+ }
+ } else {
+ run_one_opecode();
+ }
+//#endif
+ }
+ return first_icount - icount;
+ }
+}
+
+void MC6801::run_one_opecode()
+{
+ if(wai_state & (MC6800_WAI | HD6301_SLP)) {
+ increment_counter(1);
+ } else {
+ uint8_t ireg = M_RDOP(PCD);
+ prevpc = PC;
+ PC++;
+ insn(ireg);
+ increment_counter(cycles[ireg]);
+ }
+
+ // check interrupt
+ if(int_state & NMI_REQ_BIT) {
+ wai_state &= ~HD6301_SLP;
+ int_state &= ~NMI_REQ_BIT;
+ enter_interrupt(0xfffc);
+ } else if(int_state & INT_REQ_BIT) {
+ wai_state &= ~HD6301_SLP;
+ if(!(CC & 0x10)) {
+ int_state &= ~INT_REQ_BIT;
+ enter_interrupt(0xfff8);
+ }
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ } else if((tcsr & (TCSR_EICI | TCSR_ICF)) == (TCSR_EICI | TCSR_ICF)) {
+ wai_state &= ~HD6301_SLP;
+ if(!(CC & 0x10)) {
+ TAKE_ICI;
+ }
+ } else if((tcsr & (TCSR_EOCI | TCSR_OCF)) == (TCSR_EOCI | TCSR_OCF)) {
+ wai_state &= ~HD6301_SLP;
+ if(!(CC & 0x10)) {
+ TAKE_OCI;
+ }
+ } else if((tcsr & (TCSR_ETOI | TCSR_TOF)) == (TCSR_ETOI | TCSR_TOF)) {
+ wai_state &= ~HD6301_SLP;
+ if(!(CC & 0x10)) {
+ TAKE_TOI;
+ }
+ } else if(((trcsr & (TRCSR_RIE | TRCSR_RDRF)) == (TRCSR_RIE | TRCSR_RDRF)) ||
+ ((trcsr & (TRCSR_RIE | TRCSR_ORFE)) == (TRCSR_RIE | TRCSR_ORFE)) ||
+ ((trcsr & (TRCSR_TIE | TRCSR_TDRE)) == (TRCSR_TIE | TRCSR_TDRE))) {
+ wai_state &= ~HD6301_SLP;
+ if(!(CC & 0x10)) {
+ TAKE_SCI;
+ }
+//#endif
+ }
+}
+
+int MC6801::debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len)
+{
+ uint8_t ops[4];
+ for(int i = 0; i < 4; i++) {
+ int wait;
+ ops[i] = d_mem_stored->read_data8w(pc + i, &wait);
+ }
+ return Dasm680x(6801, buffer, pc, ops, ops, d_debugger->first_symbol);
+ return 0;
+}
+
+void MC6801::insn(uint8_t code)
+{
+ switch(code) {
+ case 0x00: illegal(); break;
+ case 0x01: nop(); break;
+ case 0x02: illegal(); break;
+ case 0x03: illegal(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0x04: lsrd(); break;
+ case 0x05: asld(); break;
+//#else
+// case 0x04: illegal(); break;
+// case 0x05: illegal(); break;
+//#endif
+ case 0x06: tap(); break;
+ case 0x07: tpa(); break;
+ case 0x08: inx(); break;
+ case 0x09: dex(); break;
+ case 0x0a: clv(); break;
+ case 0x0b: sev(); break;
+ case 0x0c: clc(); break;
+ case 0x0d: sec(); break;
+ case 0x0e: cli(); break;
+ case 0x0f: sei(); break;
+ case 0x10: sba(); break;
+ case 0x11: cba(); break;
+//#if defined(HAS_HD6301)
+// case 0x12: undoc1(); break;
+// case 0x13: undoc2(); break;
+//#else
+ case 0x12: illegal(); break;
+ case 0x13: illegal(); break;
+//#endif
+ case 0x14: illegal(); break;
+ case 0x15: illegal(); break;
+ case 0x16: tab(); break;
+ case 0x17: tba(); break;
+//#if defined(HAS_HD6301)
+// case 0x18: xgdx(); break;
+//#else
+ case 0x18: illegal(); break;
+//#endif
+ case 0x19: daa(); break;
+//#if defined(HAS_HD6301)
+// case 0x1a: slp(); break;
+//#else
+ case 0x1a: illegal(); break;
+//#endif
+ case 0x1b: aba(); break;
+ case 0x1c: illegal(); break;
+ case 0x1d: illegal(); break;
+ case 0x1e: illegal(); break;
+ case 0x1f: illegal(); break;
+ case 0x20: bra(); break;
+ case 0x21: brn(); break;
+ case 0x22: bhi(); break;
+ case 0x23: bls(); break;
+ case 0x24: bcc(); break;
+ case 0x25: bcs(); break;
+ case 0x26: bne(); break;
+ case 0x27: beq(); break;
+ case 0x28: bvc(); break;
+ case 0x29: bvs(); break;
+ case 0x2a: bpl(); break;
+ case 0x2b: bmi(); break;
+ case 0x2c: bge(); break;
+ case 0x2d: blt(); break;
+ case 0x2e: bgt(); break;
+ case 0x2f: ble(); break;
+ case 0x30: tsx(); break;
+ case 0x31: ins(); break;
+ case 0x32: pula(); break;
+ case 0x33: pulb(); break;
+ case 0x34: des(); break;
+ case 0x35: txs(); break;
+ case 0x36: psha(); break;
+ case 0x37: pshb(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0x38: pulx(); break;
+//#else
+// case 0x38: illegal(); break;
+//#endif
+ case 0x39: rts(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0x3a: abx(); break;
+//#else
+// case 0x3a: illegal(); break;
+//#endif
+ case 0x3b: rti(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0x3c: pshx(); break;
+ case 0x3d: mul(); break;
+//#else
+// case 0x3c: illegal(); break;
+// case 0x3d: illegal(); break;
+//#endif
+ case 0x3e: wai(); break;
+ case 0x3f: swi(); break;
+ case 0x40: nega(); break;
+ case 0x41: illegal(); break;
+ case 0x42: illegal(); break;
+ case 0x43: coma(); break;
+ case 0x44: lsra(); break;
+ case 0x45: illegal(); break;
+ case 0x46: rora(); break;
+ case 0x47: asra(); break;
+ case 0x48: asla(); break;
+ case 0x49: rola(); break;
+ case 0x4a: deca(); break;
+ case 0x4b: illegal(); break;
+ case 0x4c: inca(); break;
+ case 0x4d: tsta(); break;
+ case 0x4e: illegal(); break;
+ case 0x4f: clra(); break;
+ case 0x50: negb(); break;
+ case 0x51: illegal(); break;
+ case 0x52: illegal(); break;
+ case 0x53: comb(); break;
+ case 0x54: lsrb(); break;
+ case 0x55: illegal(); break;
+ case 0x56: rorb(); break;
+ case 0x57: asrb(); break;
+ case 0x58: aslb(); break;
+ case 0x59: rolb(); break;
+ case 0x5a: decb(); break;
+ case 0x5b: illegal(); break;
+ case 0x5c: incb(); break;
+ case 0x5d: tstb(); break;
+ case 0x5e: illegal(); break;
+ case 0x5f: clrb(); break;
+ case 0x60: neg_ix(); break;
+//#if defined(HAS_HD6301)
+// case 0x61: aim_ix(); break;
+// case 0x62: oim_ix(); break;
+//#else
+ case 0x61: illegal(); break;
+ case 0x62: illegal(); break;
+//#endif
+ case 0x63: com_ix(); break;
+ case 0x64: lsr_ix(); break;
+//#if defined(HAS_HD6301)
+// case 0x65: eim_ix(); break;
+//#else
+ case 0x65: illegal(); break;
+//#endif
+ case 0x66: ror_ix(); break;
+ case 0x67: asr_ix(); break;
+ case 0x68: asl_ix(); break;
+ case 0x69: rol_ix(); break;
+ case 0x6a: dec_ix(); break;
+//#if defined(HAS_HD6301)
+// case 0x6b: tim_ix(); break;
+//#else
+ case 0x6b: illegal(); break;
+//#endif
+ case 0x6c: inc_ix(); break;
+ case 0x6d: tst_ix(); break;
+ case 0x6e: jmp_ix(); break;
+ case 0x6f: clr_ix(); break;
+ case 0x70: neg_ex(); break;
+//#if defined(HAS_HD6301)
+// case 0x71: aim_di(); break;
+// case 0x72: oim_di(); break;
+//#elif defined(HAS_MB8861)
+// case 0x71: nim_ix(); break;
+// case 0x72: oim_ix_mb8861(); break;
+//#else
+ case 0x71: illegal(); break;
+ case 0x72: illegal(); break;
+//#endif
+ case 0x73: com_ex(); break;
+ case 0x74: lsr_ex(); break;
+//#if defined(HAS_HD6301)
+// case 0x75: eim_di(); break;
+//#elif defined(HAS_MB8861)
+// case 0x75: xim_ix(); break;
+//#else
+ case 0x75: illegal(); break;
+//#endif
+ case 0x76: ror_ex(); break;
+ case 0x77: asr_ex(); break;
+ case 0x78: asl_ex(); break;
+ case 0x79: rol_ex(); break;
+ case 0x7a: dec_ex(); break;
+//#if defined(HAS_HD6301)
+// case 0x7b: tim_di(); break;
+//#elif defined(HAS_MB8861)
+// case 0x7b: tmm_ix(); break;
+//#else
+ case 0x7b: illegal(); break;
+//#endif
+ case 0x7c: inc_ex(); break;
+ case 0x7d: tst_ex(); break;
+ case 0x7e: jmp_ex(); break;
+ case 0x7f: clr_ex(); break;
+ case 0x80: suba_im(); break;
+ case 0x81: cmpa_im(); break;
+ case 0x82: sbca_im(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0x83: subd_im(); break;
+//#else
+// case 0x83: illegal(); break;
+//#endif
+ case 0x84: anda_im(); break;
+ case 0x85: bita_im(); break;
+ case 0x86: lda_im(); break;
+ case 0x87: sta_im(); break;
+ case 0x88: eora_im(); break;
+ case 0x89: adca_im(); break;
+ case 0x8a: ora_im(); break;
+ case 0x8b: adda_im(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0x8c: cpx_im (); break;
+//#else
+// case 0x8c: cmpx_im(); break;
+//#endif
+ case 0x8d: bsr(); break;
+ case 0x8e: lds_im(); break;
+ case 0x8f: sts_im(); break;
+ case 0x90: suba_di(); break;
+ case 0x91: cmpa_di(); break;
+ case 0x92: sbca_di(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0x93: subd_di(); break;
+//#else
+// case 0x93: illegal(); break;
+//#endif
+ case 0x94: anda_di(); break;
+ case 0x95: bita_di(); break;
+ case 0x96: lda_di(); break;
+ case 0x97: sta_di(); break;
+ case 0x98: eora_di(); break;
+ case 0x99: adca_di(); break;
+ case 0x9a: ora_di(); break;
+ case 0x9b: adda_di(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0x9c: cpx_di (); break;
+//#else
+// case 0x9c: cmpx_di(); break;
+//#endif
+ case 0x9d: jsr_di(); break;
+ case 0x9e: lds_di(); break;
+ case 0x9f: sts_di(); break;
+ case 0xa0: suba_ix(); break;
+ case 0xa1: cmpa_ix(); break;
+ case 0xa2: sbca_ix(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0xa3: subd_ix(); break;
+//#else
+// case 0xa3: illegal(); break;
+//#endif
+ case 0xa4: anda_ix(); break;
+ case 0xa5: bita_ix(); break;
+ case 0xa6: lda_ix(); break;
+ case 0xa7: sta_ix(); break;
+ case 0xa8: eora_ix(); break;
+ case 0xa9: adca_ix(); break;
+ case 0xaa: ora_ix(); break;
+ case 0xab: adda_ix(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0xac: cpx_ix (); break;
+//#else
+// case 0xac: cmpx_ix(); break;
+//#endif
+ case 0xad: jsr_ix(); break;
+ case 0xae: lds_ix(); break;
+ case 0xaf: sts_ix(); break;
+ case 0xb0: suba_ex(); break;
+ case 0xb1: cmpa_ex(); break;
+ case 0xb2: sbca_ex(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0xb3: subd_ex(); break;
+//#else
+// case 0xb3: illegal(); break;
+//#endif
+ case 0xb4: anda_ex(); break;
+ case 0xb5: bita_ex(); break;
+ case 0xb6: lda_ex(); break;
+ case 0xb7: sta_ex(); break;
+ case 0xb8: eora_ex(); break;
+ case 0xb9: adca_ex(); break;
+ case 0xba: ora_ex(); break;
+ case 0xbb: adda_ex(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0xbc: cpx_ex (); break;
+//#else
+// case 0xbc: cmpx_ex(); break;
+//#endif
+ case 0xbd: jsr_ex(); break;
+ case 0xbe: lds_ex(); break;
+ case 0xbf: sts_ex(); break;
+ case 0xc0: subb_im(); break;
+ case 0xc1: cmpb_im(); break;
+ case 0xc2: sbcb_im(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0xc3: addd_im(); break;
+//#else
+// case 0xc3: illegal(); break;
+//#endif
+ case 0xc4: andb_im(); break;
+ case 0xc5: bitb_im(); break;
+ case 0xc6: ldb_im(); break;
+ case 0xc7: stb_im(); break;
+ case 0xc8: eorb_im(); break;
+ case 0xc9: adcb_im(); break;
+ case 0xca: orb_im(); break;
+ case 0xcb: addb_im(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0xcc: ldd_im(); break;
+ case 0xcd: std_im(); break;
+//#else
+// case 0xcc: illegal(); break;
+// case 0xcd: illegal(); break;
+//#endif
+ case 0xce: ldx_im(); break;
+ case 0xcf: stx_im(); break;
+ case 0xd0: subb_di(); break;
+ case 0xd1: cmpb_di(); break;
+ case 0xd2: sbcb_di(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0xd3: addd_di(); break;
+//#else
+// case 0xd3: illegal(); break;
+//#endif
+ case 0xd4: andb_di(); break;
+ case 0xd5: bitb_di(); break;
+ case 0xd6: ldb_di(); break;
+ case 0xd7: stb_di(); break;
+ case 0xd8: eorb_di(); break;
+ case 0xd9: adcb_di(); break;
+ case 0xda: orb_di(); break;
+ case 0xdb: addb_di(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0xdc: ldd_di(); break;
+ case 0xdd: std_di(); break;
+//#else
+// case 0xdc: illegal(); break;
+// case 0xdd: illegal(); break;
+//#endif
+ case 0xde: ldx_di(); break;
+ case 0xdf: stx_di(); break;
+ case 0xe0: subb_ix(); break;
+ case 0xe1: cmpb_ix(); break;
+ case 0xe2: sbcb_ix(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0xe3: addd_ix(); break;
+//#else
+// case 0xe3: illegal(); break;
+//#endif
+ case 0xe4: andb_ix(); break;
+ case 0xe5: bitb_ix(); break;
+ case 0xe6: ldb_ix(); break;
+ case 0xe7: stb_ix(); break;
+ case 0xe8: eorb_ix(); break;
+ case 0xe9: adcb_ix(); break;
+ case 0xea: orb_ix(); break;
+ case 0xeb: addb_ix(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0xec: ldd_ix(); break;
+ case 0xed: std_ix(); break;
+//#elif defined(HAS_MB8861)
+// case 0xec: adx_im(); break;
+// case 0xed: illegal(); break;
+//#else
+// case 0xec: illegal(); break;
+// case 0xed: illegal(); break;
+//#endif
+ case 0xee: ldx_ix(); break;
+ case 0xef: stx_ix(); break;
+ case 0xf0: subb_ex(); break;
+ case 0xf1: cmpb_ex(); break;
+ case 0xf2: sbcb_ex(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0xf3: addd_ex(); break;
+//#else
+// case 0xf3: illegal(); break;
+//#endif
+ case 0xf4: andb_ex(); break;
+ case 0xf5: bitb_ex(); break;
+ case 0xf6: ldb_ex(); break;
+ case 0xf7: stb_ex(); break;
+ case 0xf8: eorb_ex(); break;
+ case 0xf9: adcb_ex(); break;
+ case 0xfa: orb_ex(); break;
+ case 0xfb: addb_ex(); break;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ case 0xfc: ldd_ex(); break;
+ case 0xfd: std_ex(); break;
+//#elif defined(HAS_MB8861)
+// case 0xfc: adx_ex(); break;
+// case 0xfd: illegal(); break;
+//#else
+// case 0xfc: illegal(); break;
+// case 0xfd: illegal(); break;
+//#endif
+ case 0xfe: ldx_ex(); break;
+ case 0xff: stx_ex(); break;
+#if defined(_MSC_VER) && (_MSC_VER >= 1200)
+ default: __assume(0);
+#endif
+ }
+}
+
+/* $04 LSRD inherent -0*-* */
+void MC6801::lsrd()
+{
+ uint16_t t;
+ CLR_NZC;
+ t = D;
+ CC |= (t & 0x0001);
+ t >>= 1;
+ SET_Z16(t);
+ D = t;
+}
+
+/* $05 ASLD inherent ?**** */
+void MC6801::asld()
+{
+ int r;
+ uint16_t t;
+ t = D;
+ r = t << 1;
+ CLR_NZVC;
+ SET_FLAGS16(t, t, r);
+ D = r;
+}
+/* $38 PULX inherent ----- */
+void MC6801::pulx()
+{
+ PULLWORD(pX);
+}
+
+/* $3a ABX inherent ----- */
+void MC6801::abx()
+{
+ X += B;
+}
+/* $3c PSHX inherent ----- */
+void MC6801::pshx()
+{
+ PUSHWORD(pX);
+}
+
+/* $3d MUL inherent --*-@ */
+void MC6801::mul()
+{
+ uint16_t t;
+ t = A*B;
+ CLR_C;
+ if(t & 0x80) SEC;
+ D = t;
+}
+/* $83 SUBD immediate -**** */
+void MC6801::subd_im()
+{
+ uint32_t r, d;
+ pair_t b;
+ IMMWORD(b);
+ d = D;
+ r = d - b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+ D = r;
+}
+
+/* $8c CPX immediate -**** (6801) */
+void MC6801::cpx_im()
+{
+ uint32_t r, d;
+ pair_t b;
+ IMMWORD(b);
+ d = X;
+ r = d - b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+}
+
+/* $93 SUBD direct -**** */
+void MC6801::subd_di()
+{
+ uint32_t r, d;
+ pair_t b;
+ DIRWORD(b);
+ d = D;
+ r = d - b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+ D = r;
+}
+
+/* $9c CPX direct -**** (6801) */
+void MC6801::cpx_di()
+{
+ uint32_t r, d;
+ pair_t b;
+ DIRWORD(b);
+ d = X;
+ r = d - b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+}
+/* $a3 SUBD indexed -**** */
+void MC6801::subd_ix()
+{
+ uint32_t r, d;
+ pair_t b;
+ IDXWORD(b);
+ d = D;
+ r = d - b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+ D = r;
+}
+
+/* $ac CPX indexed -**** (6801)*/
+void MC6801::cpx_ix()
+{
+ uint32_t r, d;
+ pair_t b;
+ IDXWORD(b);
+ d = X;
+ r = d - b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+}
+
+/* $b3 SUBD extended -**** */
+void MC6801::subd_ex()
+{
+ uint32_t r, d;
+ pair_t b;
+ EXTWORD(b);
+ d = D;
+ r = d - b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+ D = r;
+}
+
+/* $bc CPX extended -**** (6801) */
+void MC6801::cpx_ex()
+{
+ uint32_t r, d;
+ pair_t b;
+ EXTWORD(b);
+ d = X;
+ r = d - b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+}
+
+/* $c3 ADDD immediate -**** */
+void MC6801::addd_im()
+{
+ uint32_t r, d;
+ pair_t b;
+ IMMWORD(b);
+ d = D;
+ r = d + b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+ D = r;
+}
+
+/* $CC LDD immediate -**0- */
+void MC6801::ldd_im()
+{
+ IMMWORD(pD);
+ CLR_NZV;
+ SET_NZ16(D);
+}
+
+/* is this a legal instruction? */
+/* $cd STD immediate -**0- */
+void MC6801::std_im()
+{
+ IMM16;
+ CLR_NZV;
+ SET_NZ16(D);
+ WM16(EAD, &pD);
+}
+
+/* $d3 ADDD direct -**** */
+void MC6801::addd_di()
+{
+ uint32_t r, d;
+ pair_t b;
+ DIRWORD(b);
+ d = D;
+ r = d + b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+ D = r;
+}
+
+/* $dc LDD direct -**0- */
+void MC6801::ldd_di()
+{
+ DIRWORD(pD);
+ CLR_NZV;
+ SET_NZ16(D);
+}
+
+/* $dd STD direct -**0- */
+void MC6801::std_di()
+{
+ DIRECT;
+ CLR_NZV;
+ SET_NZ16(D);
+ WM16(EAD, &pD);
+}
+
+/* $e3 ADDD indexed -**** */
+void MC6801::addd_ix()
+{
+ uint32_t r, d;
+ pair_t b;
+ IDXWORD(b);
+ d = D;
+ r = d + b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+ D = r;
+}
+
+/* $ec LDD indexed -**0- */
+void MC6801::ldd_ix()
+{
+ IDXWORD(pD);
+ CLR_NZV;
+ SET_NZ16(D);
+}
+
+/* $ed STD indexed -**0- */
+void MC6801::std_ix()
+{
+ INDEXED;
+ CLR_NZV;
+ SET_NZ16(D);
+ WM16(EAD, &pD);
+}
+
+/* $f3 ADDD extended -**** */
+void MC6801::addd_ex()
+{
+ uint32_t r, d;
+ pair_t b;
+ EXTWORD(b);
+ d = D;
+ r = d + b.d;
+ CLR_NZVC;
+ SET_FLAGS16(d, b.d, r);
+ D = r;
+}
+
+/* $fc LDD extended -**0- */
+void MC6801::ldd_ex()
+{
+ EXTWORD(pD);
+ CLR_NZV;
+ SET_NZ16(D);
+}
+
+/* $fd STD extended -**0- */
+void MC6801::std_ex()
+{
+ EXTENDED;
+ CLR_NZV;
+ SET_NZ16(D);
+ WM16(EAD, &pD);
+}
+
+#define STATE_VERSION 1
+
+void MC6801::save_state(FILEIO* state_fio)
+{
+ state_fio->FputUint32(STATE_VERSION);
+ state_fio->FputInt32(this_device_id);
+
+ state_fio->FputUint32(pc.d);
+ state_fio->FputUint16(prevpc);
+ state_fio->FputUint32(sp.d);
+ state_fio->FputUint32(ix.d);
+ state_fio->FputUint32(acc_d.d);
+ state_fio->FputUint32(ea.d);
+ state_fio->FputUint8(cc);
+ state_fio->FputInt32(wai_state);
+ state_fio->FputInt32(int_state);
+ state_fio->FputInt32(icount);
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ for(int i = 0; i < 4; i++) {
+ state_fio->FputUint8(port[i].wreg);
+ state_fio->FputUint8(port[i].rreg);
+ state_fio->FputUint8(port[i].ddr);
+ state_fio->FputUint8(port[i].latched_data);
+ state_fio->FputBool(port[i].latched);
+ state_fio->FputBool(port[i].first_write);
+ }
+ state_fio->FputUint8(p3csr);
+ state_fio->FputBool(p3csr_is3_flag_read);
+ state_fio->FputBool(sc1_state);
+ state_fio->FputBool(sc2_state);
+ state_fio->FputUint32(counter.d);
+ state_fio->FputUint32(output_compare.d);
+ state_fio->FputUint32(timer_over.d);
+ state_fio->FputUint8(tcsr);
+ state_fio->FputUint8(pending_tcsr);
+ state_fio->FputUint16(input_capture);
+//#ifdef HAS_HD6301
+// state_fio->FputUint16(latch09);
+//#endif
+ state_fio->FputUint32(timer_next);
+ recv_buffer->save_state((void *)state_fio);
+ state_fio->FputUint8(trcsr);
+ state_fio->FputUint8(rdr);
+ state_fio->FputUint8(tdr);
+ state_fio->FputBool(trcsr_read_tdre);
+ state_fio->FputBool(trcsr_read_orfe);
+ state_fio->FputBool(trcsr_read_rdrf);
+ state_fio->FputUint8(rmcr);
+ state_fio->FputInt32(sio_counter);
+ state_fio->FputUint8(ram_ctrl);
+ state_fio->Fwrite(ram, sizeof(ram), 1);
+//#endif
+}
+
+bool MC6801::load_state(FILEIO* state_fio)
+{
+ if(state_fio->FgetUint32() != STATE_VERSION) {
+ return false;
+ }
+ if(state_fio->FgetInt32() != this_device_id) {
+ return false;
+ }
+ pc.d = state_fio->FgetUint32();
+ prevpc = state_fio->FgetUint16();
+ sp.d = state_fio->FgetUint32();
+ ix.d = state_fio->FgetUint32();
+ acc_d.d = state_fio->FgetUint32();
+ ea.d = state_fio->FgetUint32();
+ cc = state_fio->FgetUint8();
+ wai_state = state_fio->FgetInt32();
+ int_state = state_fio->FgetInt32();
+ icount = state_fio->FgetInt32();
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ for(int i = 0; i < 4; i++) {
+ port[i].wreg = state_fio->FgetUint8();
+ port[i].rreg = state_fio->FgetUint8();
+ port[i].ddr = state_fio->FgetUint8();
+ port[i].latched_data = state_fio->FgetUint8();
+ port[i].latched = state_fio->FgetBool();
+ port[i].first_write = state_fio->FgetBool();
+ }
+ p3csr = state_fio->FgetUint8();
+ p3csr_is3_flag_read = state_fio->FgetBool();
+ sc1_state = state_fio->FgetBool();
+ sc2_state = state_fio->FgetBool();
+ counter.d = state_fio->FgetUint32();
+ output_compare.d = state_fio->FgetUint32();
+ timer_over.d = state_fio->FgetUint32();
+ tcsr = state_fio->FgetUint8();
+ pending_tcsr = state_fio->FgetUint8();
+ input_capture = state_fio->FgetUint16();
+//#ifdef HAS_HD6301
+// latch09 = state_fio->FgetUint16();
+//#endif
+ timer_next = state_fio->FgetUint32();
+ if(!recv_buffer->load_state((void *)state_fio)) {
+ return false;
+ }
+ trcsr = state_fio->FgetUint8();
+ rdr = state_fio->FgetUint8();
+ tdr = state_fio->FgetUint8();
+ trcsr_read_tdre = state_fio->FgetBool();
+ trcsr_read_orfe = state_fio->FgetBool();
+ trcsr_read_rdrf = state_fio->FgetBool();
+ rmcr = state_fio->FgetUint8();
+ sio_counter = state_fio->FgetInt32();
+ ram_ctrl = state_fio->FgetUint8();
+ state_fio->Fread(ram, sizeof(ram), 1);
+//#endif
+ return true;
+}
--- /dev/null
+/*
+ Skelton for retropc emulator
+
+ Origin : MAME 0.142
+ Author : Takeda.Toshiya
+ Date : 2011.04.23-
+
+ [ MC6801 ]
+*/
+
+#ifndef _MC6801_H_
+#define _MC6801_H_
+
+//#include "vm.h"
+//#include "../emu.h"
+#include "mc6800.h"
+#include "device.h"
+
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+#define SIG_MC6801_PORT_1 0
+#define SIG_MC6801_PORT_2 1
+#define SIG_MC6801_PORT_3 2
+#define SIG_MC6801_PORT_4 3
+#define SIG_MC6801_PORT_3_SC1 4
+#define SIG_MC6801_PORT_3_SC2 5
+#define SIG_MC6801_SIO_RECV 6
+
+class DEBUGGER;
+class FIFO;
+//#endif
+class MC6801 : public MC6800
+{
+private:
+protected:
+ const int RMCR_SS[4] = { 16, 128, 1024, 4096 };
+#define XX 5 // invalid opcode unknown cc
+ const uint8_t cycles[256] = {
+//#elif defined(HAS_MC6801)
+ XX, 2,XX,XX, 3, 3, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2,
+ 2, 2,XX,XX,XX,XX, 2, 2,XX, 2,XX, 2,XX,XX,XX,XX,
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 4, 4, 3, 3, 3, 3, 5, 5, 3,10, 4,10, 9,12,
+ 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
+ 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
+ 6,XX,XX, 6, 6,XX, 6, 6, 6, 6, 6,XX, 6, 6, 3, 6,
+ 6,XX,XX, 6, 6,XX, 6, 6, 6, 6, 6,XX, 6, 6, 3, 6,
+ 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 4, 6, 3, 3,
+ 3, 3, 3, 5, 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 4, 4,
+ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 5, 5,
+ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 5, 5,
+ 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 3,XX, 3, 3,
+ 3, 3, 3, 5, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4,
+ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
+ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5
+ };
+#undef XX
+ //#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ // data
+ struct {
+ uint8_t wreg;
+ uint8_t rreg;
+ uint8_t ddr;
+ uint8_t latched_data;
+ bool latched;
+ // output signals
+ outputs_t outputs;
+ bool first_write;
+ } port[4];
+
+ uint8_t p3csr;
+ bool p3csr_is3_flag_read;
+ bool sc1_state;
+ bool sc2_state;
+
+ // timer
+ pair_t counter;
+ pair_t output_compare;
+ pair_t timer_over;
+ uint8_t tcsr;
+ uint8_t pending_tcsr;
+ uint16_t input_capture;
+//#ifdef HAS_HD6301
+// uint16_t latch09;
+//#endif
+ uint32_t timer_next;
+
+ // serial i/o
+ outputs_t outputs_sio;
+ FIFO *recv_buffer;
+ uint8_t trcsr, rdr, tdr;
+ bool trcsr_read_tdre, trcsr_read_orfe, trcsr_read_rdrf;
+ uint8_t rmcr;
+ int sio_counter;
+
+ // memory controller
+ uint8_t ram_ctrl;
+ uint8_t ram[128];
+
+
+ uint32_t mc6801_io_r(uint32_t offset);
+ virtual void mc6801_io_w(uint32_t offset, uint32_t data);
+ void increment_counter(int amount);
+
+ uint32_t RM(uint32_t Addr) override;
+ void WM(uint32_t Addr, uint32_t Value) override;
+
+ void run_one_opecode() override;
+
+ void insn(uint8_t code) override;
+ void abx();
+ void addd_di();
+ void addd_ex();
+ void addd_im();
+ void addd_ix();
+ void asld();
+ void ldd_di();
+ void ldd_ex();
+ void ldd_im();
+ void ldd_ix();
+ void lsrd();
+ void mul();
+ void pshx();
+ void pulx();
+ void std_di();
+ void std_ex();
+ void std_im();
+ void std_ix();
+ void subd_di();
+ void subd_ex();
+ void subd_im();
+ void subd_ix();
+ void cpx_di();
+ void cpx_ex();
+ void cpx_im();
+ void cpx_ix();
+
+//#endif
+public:
+ MC6801(VM* parent_vm, EMU* parent_emu) : MC6800(parent_vm, parent_emu)
+ {
+ for(int i = 0; i < 4; i++) {
+ initialize_output_signals(&port[i].outputs);
+ port[i].wreg = port[i].rreg = 0;//0xff;
+ }
+ initialize_output_signals(&outputs_sio);
+ set_device_name(_T("MC6801 MPU"));
+ }
+ ~MC6801() {}
+ void initialize() override;
+ void release();
+ void reset() override;
+ int run(int clock) override;
+ void write_signal(int id, uint32_t data, uint32_t mask) override;
+ void save_state(FILEIO* state_fio) override;
+ bool load_state(FILEIO* state_fio) override;
+
+
+ int debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len) override;
+//#if defined(HAS_MC6801) || defined(HAS_HD6301)
+ void set_context_port1(DEVICE* device, int id, uint32_t mask, int shift)
+ {
+ register_output_signal(&port[0].outputs, device, id, mask, shift);
+ }
+ void set_context_port2(DEVICE* device, int id, uint32_t mask, int shift)
+ {
+ register_output_signal(&port[1].outputs, device, id, mask, shift);
+ }
+ void set_context_port3(DEVICE* device, int id, uint32_t mask, int shift)
+ {
+ register_output_signal(&port[2].outputs, device, id, mask, shift);
+ }
+ void set_context_port4(DEVICE* device, int id, uint32_t mask, int shift)
+ {
+ register_output_signal(&port[2].outputs, device, id, mask, shift);
+ }
+ void set_context_sio(DEVICE* device, int id)
+ {
+ register_output_signal(&outputs_sio, device, id, 0xff);
+ }
+//#endif
+};
+
+#endif
--- /dev/null
+#ifndef __MC6801_CONSTS_H__
+#define __MC6801_CONSTS_H__
+#define CT counter.w.l
+#define CTH counter.w.h
+#define CTD counter.d
+#define OC output_compare.w.l
+#define OCH output_compare.w.h
+#define OCD output_compare.d
+#define TOH timer_over.w.l
+#define TOD timer_over.d
+
+#define SET_TIMER_EVENT { \
+ timer_next = (OCD - CTD < TOD - CTD) ? OCD : TOD; \
+}
+
+#define CLEANUP_COUNTERS() { \
+ OCH -= CTH; \
+ TOH -= CTH; \
+ CTH = 0; \
+ SET_TIMER_EVENT; \
+}
+
+#define MODIFIED_counters { \
+ OCH = (OC >= CT) ? CTH : CTH + 1; \
+ SET_TIMER_EVENT; \
+}
+
+#define TCSR_OLVL 0x01
+#define TCSR_IEDG 0x02
+#define TCSR_ETOI 0x04
+#define TCSR_EOCI 0x08
+#define TCSR_EICI 0x10
+#define TCSR_TOF 0x20
+#define TCSR_OCF 0x40
+#define TCSR_ICF 0x80
+
+#define TRCSR_WU 0x01
+#define TRCSR_TE 0x02
+#define TRCSR_TIE 0x04
+#define TRCSR_RE 0x08
+#define TRCSR_RIE 0x10
+#define TRCSR_TDRE 0x20
+#define TRCSR_ORFE 0x40
+#define TRCSR_RDRF 0x80
+
+#define P3CSR_LE 0x08
+#define P3CSR_IS3_ENABLE 0x40
+#define P3CSR_IS3_FLAG 0x80
+
+/****************************************************************************/
+/* MC6801/HD6301 internal i/o port */
+/****************************************************************************/
+
+/* take interrupt */
+#define TAKE_ICI enter_interrupt(0xfff6)
+#define TAKE_OCI enter_interrupt(0xfff4)
+#define TAKE_TOI enter_interrupt(0xfff2)
+#define TAKE_SCI enter_interrupt(0xfff0)
+#define TAKE_TRAP enter_interrupt(0xffee)
+
+#endif /* __MC6801_CONSTS_H__ */
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