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drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV
author
Matt Roper
<matthew.d.roper@intel.com>
Thu, 29 Jul 2021 17:00:01 +0000
(10:00 -0700)
committer
Matt Roper
<matthew.d.roper@intel.com>
Wed, 4 Aug 2021 04:12:51 +0000
(21:12 -0700)
DG2 supports compute DSS and has the same maximum number of DSS and EU
as XeHP SDV.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Caz Yokoyama <caz.yokoyama@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link:
https://patchwork.freedesktop.org/patch/msgid/20210729170008.2836648-12-matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_sseu.c
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diff --git
a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index
3a2ff0e
..
a648818
100644
(file)
--- a/
drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/
drivers/gpu/drm/i915/gt/intel_sseu.c
@@
-145,7
+145,7
@@
static void gen12_sseu_info_init(struct intel_gt *gt)
* across the entire device. Then calculate out the DSS for each
* workload type within that software slice.
*/
- if (IS_XEHPSDV(gt->i915))
+ if (IS_
DG2(gt->i915) || IS_
XEHPSDV(gt->i915))
intel_sseu_set_info(sseu, 1, 32, 16);
else
intel_sseu_set_info(sseu, 1, 6, 16);