{
*r0 = extract32(insn, 8, 4);
*r1 = extract32(insn, 12, 4);
- *m2 = extract32(insn, 20, 12);
+ *m2 = extract32(insn, 16, 16);
}
static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2)
*c3 = extract32(insn, 20, 4);
}
-static void tci_args_rrrm(uint32_t insn,
- TCGReg *r0, TCGReg *r1, TCGReg *r2, MemOpIdx *m3)
-{
- *r0 = extract32(insn, 8, 4);
- *r1 = extract32(insn, 12, 4);
- *r2 = extract32(insn, 16, 4);
- *m3 = extract32(insn, 20, 12);
-}
-
static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, uint8_t *i3, uint8_t *i4)
{
tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
} else {
- tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
taddr = tci_uint64(regs[r2], regs[r1]);
+ oi = regs[r3];
}
do_ld_i32:
regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr);
tci_args_rrm(insn, &r0, &r1, &oi);
taddr = (uint32_t)regs[r1];
} else {
- tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
taddr = (uint32_t)regs[r2];
+ oi = regs[r3];
}
goto do_ld_i64;
case INDEX_op_qemu_ld_a64_i64:
tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
} else {
- tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
taddr = tci_uint64(regs[r2], regs[r1]);
+ oi = regs[r3];
}
do_st_i32:
tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr);
tmp64 = regs[r0];
taddr = (uint32_t)regs[r1];
} else {
- tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
tmp64 = tci_uint64(regs[r1], regs[r0]);
taddr = (uint32_t)regs[r2];
+ oi = regs[r3];
}
goto do_st_i64;
case INDEX_op_qemu_st_a64_i64:
op_name, str_r(r0), str_r(r1), oi);
break;
case 3:
- tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
- info->fprintf_func(info->stream, "%-12s %s, %s, %s, %x",
- op_name, str_r(r0), str_r(r1), str_r(r2), oi);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
+ info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
+ op_name, str_r(r0), str_r(r1),
+ str_r(r2), str_r(r3));
break;
case 4:
tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
{
tcg_insn_unit insn = 0;
- tcg_debug_assert(m2 == extract32(m2, 0, 12));
+ tcg_debug_assert(m2 == extract32(m2, 0, 16));
insn = deposit32(insn, 0, 8, op);
insn = deposit32(insn, 8, 4, r0);
insn = deposit32(insn, 12, 4, r1);
- insn = deposit32(insn, 20, 12, m2);
+ insn = deposit32(insn, 16, 16, m2);
tcg_out32(s, insn);
}
tcg_out32(s, insn);
}
-static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op,
- TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3)
-{
- tcg_insn_unit insn = 0;
-
- tcg_debug_assert(m3 == extract32(m3, 0, 12));
- insn = deposit32(insn, 0, 8, op);
- insn = deposit32(insn, 8, 4, r0);
- insn = deposit32(insn, 12, 4, r1);
- insn = deposit32(insn, 16, 4, r2);
- insn = deposit32(insn, 20, 12, m3);
- tcg_out32(s, insn);
-}
-
static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4)
{
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
} else {
- tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]);
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]);
+ tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], TCG_REG_TMP);
}
break;
case INDEX_op_qemu_ld_a64_i64: