}
/* Switch to V7M main or process stack pointer. */
-static void switch_v7m_sp(CPUARMState *env, int process)
+static void switch_v7m_sp(CPUARMState *env, bool new_spsel)
{
uint32_t tmp;
- if (env->v7m.current_sp != process) {
+ bool old_spsel = env->v7m.control & R_V7M_CONTROL_SPSEL_MASK;
+
+ if (old_spsel != new_spsel) {
tmp = env->v7m.other_sp;
env->v7m.other_sp = env->regs[13];
env->regs[13] = tmp;
- env->v7m.current_sp = process;
+
+ env->v7m.control = deposit32(env->v7m.control,
+ R_V7M_CONTROL_SPSEL_SHIFT,
+ R_V7M_CONTROL_SPSEL_LENGTH, new_spsel);
}
}
arm_log_exception(cs->exception_index);
lr = 0xfffffff1;
- if (env->v7m.current_sp)
+ if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {
lr |= 4;
+ }
if (env->v7m.exception == 0)
lr |= 8;
switch (reg) {
case 8: /* MSP */
- return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
+ return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ?
+ env->v7m.other_sp : env->regs[13];
case 9: /* PSP */
- return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
+ return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ?
+ env->regs[13] : env->v7m.other_sp;
case 16: /* PRIMASK */
return (env->daif & PSTATE_I) != 0;
case 17: /* BASEPRI */
}
break;
case 8: /* MSP */
- if (env->v7m.current_sp)
+ if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {
env->v7m.other_sp = val;
- else
+ } else {
env->regs[13] = val;
+ }
break;
case 9: /* PSP */
- if (env->v7m.current_sp)
+ if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {
env->regs[13] = val;
- else
+ } else {
env->v7m.other_sp = val;
+ }
break;
case 16: /* PRIMASK */
if (val & 1) {
}
break;
case 20: /* CONTROL */
- env->v7m.control = val & 3;
- switch_v7m_sp(env, (val & 2) != 0);
+ switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
+ env->v7m.control = val & (R_V7M_CONTROL_SPSEL_MASK |
+ R_V7M_CONTROL_NPRIV_MASK);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"
#ifndef TARGET_ARM_INTERNALS_H
#define TARGET_ARM_INTERNALS_H
+#include "hw/registerfields.h"
+
/* register banks for CPU modes */
#define BANK_USRSYS 0
#define BANK_SVC 1
*/
#define GTIMER_SCALE 16
+/* Bit definitions for the v7M CONTROL register */
+FIELD(V7M_CONTROL, NPRIV, 0, 1)
+FIELD(V7M_CONTROL, SPSEL, 1, 1)
+FIELD(V7M_CONTROL, FPCA, 2, 1)
+
/*
* For AArch64, map a given EL to an index in the banked_spsr array.
* Note that this mapping and the AArch32 mapping defined in bank_number()
static const VMStateDescription vmstate_m = {
.name = "cpu/m",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.needed = m_needed,
.fields = (VMStateField[]) {
- VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
VMSTATE_UINT32(env.v7m.control, ARMCPU),
- VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
VMSTATE_INT32(env.v7m.exception, ARMCPU),
VMSTATE_END_OF_LIST()
}